CUDA optimization strategies for compute- and memory-bound neuroimaging algorithms

As neuroimaging algorithms and technology continue to grow faster than CPU performance in complexity and image resolution, data-parallel computing methods will be increasingly important. The high performance, data-parallel architecture of modern graphical processing units (GPUs) can reduce computational times by orders of magnitude. However, its massively threaded architecture introduces challenges when GPU resources are exceeded. This paper presents optimization strategies for compute- and memory-bound algorithms for the CUDA architecture. For compute-bound algorithms, the registers are reduced through variable reuse via shared memory and the data throughput is increased through heavier thread workloads and maximizing the thread configuration for a single thread block per multiprocessor. For memory-bound algorithms, fitting the data into the fast but limited GPU resources is achieved through reorganizing the data into self-contained structures and employing a multi-pass approach. Memory latencies are reduced by selecting memory resources whose cache performance are optimized for the algorithm's access patterns. We demonstrate the strategies on two computationally expensive algorithms and achieve optimized GPU implementations that perform up to 6× faster than unoptimized ones. Compared to CPU implementations, we achieve peak GPU speedups of 129× for the 3D unbiased nonlinear image registration technique and 93× for the non-local means surface denoising algorithm.

Ferroelectric-carbon nanotube memory devices

One-dimensional ferroelectric nanostructures, carbon nanotubes (CNT) and CNT-inorganic oxides have recently been studied due to their potential applications for microelectronics. Here, we report coating of a registered array of aligned multi-wall carbon nanotubes (MWCNT) grown on silicon substrates by functional ferroelectric Pb(Zr,Ti)O3 (PZT) which produces structures suitable for commercial prototype memories. Microstructural analysis reveals the crystalline nature of PZT with small nanocrystals aligned in different directions. First-order Raman modes of MWCNT and PZT/MWCNT/n-Si show the high structural quality of CNT before and after PZT deposition at elevated temperature. PZT exists mostly in the monoclinic Cc/Cm phase, which is the origin of the high piezoelectric response in the system. Low-loss square piezoelectric hysteresis obtained for the 3D bottom-up structure confirms the switchability of the device. Current-voltage mapping of the device by conducting atomic force microscopy (c-AFM) indicates very low transient current. Fabrication and functional properties of these hybrid ferroelectric-carbon nanotubes is the first step towards miniaturization for future nanotechnology sensors, actuators, transducers and memory devices.

Multi-dimensional characterization of electrostatic surface potential computation on graphics processors

BACKGROUND

Calculating the electrostatic surface potential (ESP) of a biomolecule is critical towards understanding biomolecular function. Because of its quadratic computational complexity (as a function of the number of atoms in a molecule), there have been continual efforts to reduce its complexity either by improving the algorithm or the underlying hardware on which the calculations are performed.

RESULTS

We present the combined effect of (i) a multi-scale approximation algorithm, known as hierarchical charge partitioning (HCP), when applied to the calculation of ESP and (ii) its mapping onto a graphics processing unit (GPU). To date, most molecular modeling algorithms perform an artificial partitioning of biomolecules into a grid/lattice on the GPU. In contrast, HCP takes advantage of the natural partitioning in biomolecules, which in turn, better facilitates its mapping onto the GPU. Specifically, we characterize the effect of known GPU optimization techniques like use of shared memory. In addition, we demonstrate how the cost of divergent branching on a GPU can be amortized across algorithms like HCP in order to deliver a massive performance boon.

CONCLUSIONS

We accelerated the calculation of ESP by 25-fold solely by parallelization on the GPU. Combining GPU and HCP, resulted in a speedup of at most 1,860-fold for our largest molecular structure. The baseline for these speedups is an implementation that has been hand-tuned SSE-optimized and parallelized across 16 cores on the CPU. The use of GPU does not deteriorate the accuracy of our results.

Neural learning circuits utilizing nano-crystalline silicon transistors and memristors

Properties of neural circuits are demonstrated via SPICE simulations and their applications are discussed. The neuron and synapse subcircuits include ambipolar nano-crystalline silicon transistor and memristor device models based on measured data. Neuron circuit characteristics and the Hebbian synaptic learning rule are shown to be similar to biology. Changes in the average firing rate learning rule depending on various circuit parameters are also presented. The subcircuits are then connected into larger neural networks that demonstrate fundamental properties including associative learning and pulse coincidence detection. Learned extraction of a fundamental frequency component from noisy inputs is demonstrated. It is then shown that if the fundamental sinusoid of one neuron input is out of phase with the rest, its synaptic connection changes differently than the others. Such behavior indicates that the system can learn to detect which signals are important in the general population, and that there is a spike-timing-dependent component of the learning mechanism. Finally, future circuit design and considerations are discussed, including requirements for the memristive device.

Magnetoelectric charge trap memory

It is demonstrated that a charge-trapping layer placed in proximity to a ferromagnetic metal enables efficient electrical and optical control of the metal's magnetic properties. Retention of charge trapped inside the charge-trapping layer provides nonvolatility to the magnetoelectric effect and enhances its efficiency by an order of magnitude. As such, an engineered charge-trapping layer can be used to realize the magnetoelectric equivalent to today's pervasive charge trap flash memory technology. Moreover, by supplying trapped charges optically instead of electrically, a focused laser beam can be used to imprint the magnetic state into a continuous metal film.

Detection of charge storage on molecular thin films of tris(8-hydroxyquinoline) aluminum (Alq3) by Kelvin force microscopy: a candidate system for high storage capacity memory cells

Retention and diffusion of charge in tris(8-hydroxyquinoline) aluminum (Alq(3)) molecular thin films are investigated by injecting electrons and holes via a biased conductive atomic force microscopy tip into the Alq(3) films. After the charge injection, Kelvin force microscopy measurements reveal minimal changes with time in the spatial extent of the trapped charge domains within Alq(3) films, even for high hole and electron densities of >10(12) cm(-2). We show that this finding is consistent with the very low mobility of charge carriers in Alq(3) thin films (<10(-7) cm(2)/(Vs)) and that it can benefit from the use of Alq(3) films as nanosegmented floating gates in flash memory cells. Memory capacitors using Alq(3) molecules as the floating gate are fabricated and measured, showing durability over more than 10(4) program/erase cycles and the hysteresis window of up to 7.8 V, corresponding to stored charge densities as high as 5.4 × 10(13) cm(-2). These results demonstrate the potential for use of molecular films in high storage capacity nonvolatile memory cells.

Detuned surface plasmon resonance scattering of gold nanorods for continuous wave multilayered optical recording and readout

In a multilayered structure of absorptive optical recording media, continuous-wave laser operation is highly disadvantageous due to heavy beam extinction. For a gold nanorod based recording medium, the narrow surface plasmon resonance (SPR) profile of gold nanorods enables the variation of extinction through mulilayers by a simple detuning of the readout wavelength from the SPR peak. The level of signal extinction through the layers can then be greatly reduced, resulting more efficient readout at deeper layers. The scattering signal strength may be decreased at the detuned wavelength, but balancing these two factors results an optimal scattering peak wavelength that is specific to each layer. In this paper, we propose to use detuned SPR scattering from gold nanorods as a new mechanism for continuous-wave readout scheme on gold nanorod based multilayered optical storage. Using this detuned scattering method, readout using continuous-wave laser is demonstrated on a 16 layer optical recording medium doped with heavily distributed, randomly oriented gold nanorods. Compared to SPR on-resonant readout, this method reduced the required readout power more than one order of magnitude, with only 60 nm detuning from SPR peak. The proposed method will be highly beneficial to multilayered optical storage applications as well as applications using a continuous medium doped heavily with plasmonic nanoparticles.

Concept of a thin film memory transistor based on ZnO nanoparticles insulated by a ligand shell

In this work, we report on the synthesis and the electrical properties of ZnO nanoparticles, which differ in their organic shell. The introduction of a 2-ethylhexanoate shell instead of a common acetate shell has an impact on the accessible size of the ZnO nanoparticles and changes the electrical properties of thin films in transistors. While acetate covered ZnO particles behave as a semiconductor with an electron mobility of 0.38 cm(2) V(-1) s(-1), the 2-ethylhexanoate ligand shell inhibits a charge transport resulting in insulating films (with an average ε(r) = 9.4). These films can be reconverted to semiconductive layers by removing the ligand shell with oxygen plasma treatment or they can be used as a solution processed dielectric layer in organic transistors. Its use as dielectric allows low voltage device operation and shows potential application as a charge storage layer as needed in non-volatile memory transistors.

Multilevel data storage memory using deterministic polarization control

Multilevel non-volatile memory for high-density date storage is achieved by using the deterministic control of ferroelectric polarization. In a real ferroelectric thin-film system, eight stable and reproducible polarization states are realized (i.e., 3-bit data storage) by adjusting the displacement current. This approach can be used to triple or quadruple the memory density, even at existing feature scales.

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme.

Fabrication of arrayed Si nanowire-based nano-floating gate memory devices on flexible plastics

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.

Effect of glycerol on retention time and electrical properties of polymer bistable memory devices based on glycerol-modified PEDOT:PSS

The addition of glycerol to Poly(3,4-ethylenedioxythiophene):Poly(styrene sulfonate) (PEDOT:PSS) films affected the bipolar switching characteristics of nonvolatile polymer memory devices (PMDs). Increasing the glycerol/PEDOT:PSS ratio caused increase in the OFF-current of the PMDs, but did not affect the ON-current levels. This result demonstrates that highly-conductive current paths occur in the ON-state. The write-read-erase-read cycle test was operated > 10(5) times. And, the ON-retention time is largely dependent on the glycerol to PEDOT:PSS ratio and annealing temperature. In addition, AFM analysis on the G-PEDOT:PSS films to see how the surface morphology of G-PEDOT:PSS layer influences the retention time properties was carried out.

Stochastic memory: memory enhancement due to noise

There are certain classes of resistors, capacitors, and inductors that, when subject to a periodic input of appropriate frequency, develop hysteresis loops in their characteristic response. Here we show that the hysteresis of such memory elements can also be induced by white noise of appropriate intensity even at very low frequencies of the external driving field. We illustrate this phenomenon using a physical model of memory resistor realized by TiO(2) thin films sandwiched between metallic electrodes and discuss under which conditions this effect can be observed experimentally. We also discuss its implications on existing memory systems described in the literature and the role of colored noise.

Robust holographic storage system design

Demand is increasing daily for large data storage systems that are useful for applications in spacecraft, space satellites, and space robots, which are all exposed to radiation-rich space environment. As candidates for use in space embedded systems, holographic storage systems are promising because they can easily provided the demanded large-storage capability. Particularly, holographic storage systems, which have no rotation mechanism, are demanded because they are virtually maintenance-free. Although a holographic memory itself is an extremely robust device even in a space radiation environment, its associated lasers and drive circuit devices are vulnerable. Such vulnerabilities sometimes engendered severe problems that prevent reading of all contents of the holographic memory, which is a turn-off failure mode of a laser array. This paper therefore presents a proposal for a recovery method for the turn-off failure mode of a laser array on a holographic storage system, and describes results of an experimental demonstration.

Memory and threshold resistance switching in Ni/NiO core-shell nanowires

We report on the first controlled alternation between memory and threshold resistance switching (RS) in single Ni/NiO core-shell nanowires by setting the compliance current (I(CC)) at room temperature. The memory RS is triggered by a high I(CC), while the threshold RS appears by setting a low I(CC), and the Reset process is achieved without setting a I(CC). In combination with first-principles calculations, the physical mechanisms for the memory and threshold RS are fully discussed and attributed to the formation of an oxygen vacancy (Vo) chain conductive filament and the electrical field induced breakdown without forming a conductive filament, respectively. Migration of oxygen vacancies can be activated by appropriate Joule heating, and it is energetically favorable to form conductive chains rather than random distributions due to the Vo-Vo interaction, which results in the nonvolatile switching from the off- to the on-state. For the Reset process, large Joule heating reorders the oxygen vacancies by breaking the Vo-Vo interactions and thus rupturing the conductive filaments, which are responsible for the switching from on- to off-states. This deeper understanding of the driving mechanisms responsible for the threshold and memory RS provides guidelines for the scaling, reliability, and reproducibility of NiO-based nonvolatile memory devices.

Scalable processes for fabricating non-volatile memory devices using self-assembled 2D arrays of gold nanoparticles as charge storage nodes

We propose robust and scalable processes for the fabrication of floating gate devices using ordered arrays of 7 nm size gold nanoparticles as charge storage nodes. The proposed strategy can be readily adapted for fabricating next generation (sub-20 nm node) non-volatile memory devices.

Graphene flash memory

Graphene's single atomic layer of sp(2) carbon has recently garnered much attention for its potential use in electronic applications. Here, we report a memory application for graphene, which we call graphene flash memory (GFM). GFM has the potential to exceed the performance of current flash memory technology by utilizing the intrinsic properties of graphene, such as high density of states, high work function, and low dimensionality. To this end, we have grown large-area graphene sheets by chemical vapor deposition and integrated them into a floating gate structure. GFM displays a wide memory window of ∼6 V at significantly low program/erase voltages of ±7 V. GFM also shows a long retention time of more than 10 years at room temperature. Additionally, simulations suggest that GFM suffers very little from cell-to-cell interference, potentially enabling scaling down far beyond current state-of-the-art flash memory devices.

Spin-wave interference patterns created by spin-torque nano-oscillators for memory and computation

Magnetization dynamics in nanomagnets has attracted broad interest since it was predicted that a dc current flowing through a thin magnetic layer can create spin-wave excitations. These excitations are due to spin momentum transfer, a transfer of spin angular momentum between conduction electrons and the background magnetization, that enables new types of information processing. Here we show how arrays of spin-torque nano-oscillators can create propagating spin-wave interference patterns of use for memory and computation. Memristic transponders distributed on the thin film respond to threshold tunnel magnetoresistance values, thereby allowing spin-wave detection and creating new excitation patterns. We show how groups of transponders create resonant (reverberating) spin-wave interference patterns that may be used for polychronous wave computation and information storage.

Lognormal switching times for titanium dioxide bipolar memristors: origin and resolution

We measured the switching time statistics for a TiO(2) memristor and found that they followed a lognormal distribution, which is a potentially serious problem for computer memory and data storage applications. We examined the underlying physical phenomena that determine the switching statistics and proposed a simple analytical model for the distribution based on the drift/diffusion equation and previously measured nonlinear drift behavior. We designed a closed-loop switching protocol that dramatically narrows the time distribution, which can significantly improve memory circuit performance and reliability.

High temperature polyimide containing anthracene moiety and its structure, interface, and nonvolatile memory behavior

A high temperature polyimide bearing anthracene moieties, poly(3,3'-di(9-anthracenemethoxy)-4,4'-biphenylene hexafluoroisopropylidenediphthalimide) (6F-HAB-AM PI) was synthesized. The polymer exhibits excellent thermal stability up to around 410 °C. This polymer is amorphous but orients preferentially in the plane of nanoscale thin films. In device fabrications of its nanoscale thin films with metal top and bottom electrodes, no diffusion of the metal atoms or ions between the polymer and electrodes was found; however, the aluminum bottom electrode had somewhat undergone oxide layer (about 1.2 nm thick) formation at the surface during the post polymer layer formation process, which was confirmed to have no significant influence on the device performance. The polymer thin film exhibited excellent unipolar and bipolar switching behaviors over a very small voltage range, less than ±2 V. Further, the PI films show repeatable writing, reading, and erasing ability with long reliability and high ON/OFF current ratio (up to 10(7)) in air ambient conditions as well as even at temperatures up to 200 °C.

Considerations for the implementation of 2D protein based memory

The effect of double erasure on Monolayer Bacteriorhodopsin (BR) protein films after photonic excitation to the ultra stable Q-state is studied. It was found that the pronounced emission of 755 nm light occurs only as the protein is made to transition from the Q-state to the ground state via irradiation with blue light. Requirements for the implementation of a next generation Protein-Based Memory (PBM) device utilizing monolayer BR films are considered. The finite element method was used to simulate the optical intensity distribution of nano-aperture waveguides for Red (650 nm), Green (510 nm) and Blue (475 nm) light to analyze the utility of nanoaperture transducers for use in a Protein Based Memory device. The minimum output power required to induce a photochromic transition in BR is calculated to be between 20 nW and 27 nW on a 30 nm spot depending upon the operating wavelength.

Atomic vapor quantum memory for a photonic polarization qubit

We report an experimental realization of an atomic vapor quantum memory for the photonic polarization qubit. The performance of the quantum memory for the polarization qubit, realized with electromagnetically-induced transparency in two spatially separated ensembles of warm Rubidium atoms in a single vapor cell, has been characterized with quantum process tomography. The process fidelity better than 0.91 for up to 16 μs of storage time has been achieved.

Polymeric memory elements and logic circuits that store multiple bit states

The ever-increasing flow of information requires new approaches for high-density data storage (HDDS). Here, we present a novel solution that incorporates the easily accessible polymer poly(3,4-ethylenedioxythiophene) (PEDOT) with multistate memory. The electrical addressable polymer is able to store up to five different memory states, which are stable up to 20 min. The observed memory states are generated by the optical output signature of the PEDOT deposited on indium tin oxide (ITO) coated glass, upon applying specific electrical inputs. Moreover, the demonstrated platforms can be represented by a general logic circuit, which allows the construction of multistate memory, such as flip-flops and flip-flap-flop logic circuits.

Novel nonvolatile memory with multibit storage based on a ZnO nanowire transistor

We demonstrate a room temperature processed ferroelectric (FE) nonvolatile memory based on a ZnO nanowire (NW) FET where the NW channel is coated with FE nanoparticles. A single device exhibits excellent memory characteristics with the large modulation in channel conductance between ON and OFF states exceeding 10(4), a long retention time of over 4 × 10(4) s, and multibit memory storage ability. Our findings provide a viable way to create new functional high-density nonvolatile memory devices compatible with simple processing techniques at low temperature for flexible devices made on plastic substrates.