Pass-Transistor Logic Circuits Based on Wafer-Scale 2D Semiconductors

High-Performance and Low-Power Applications of n- and p-Type Symmetrically Ultrascaled Pentagonal CX2 Transistors

The disparity in transport properties between n-type and p-type transistors has hindered the advancement of complementary metal-oxide-semiconductor (CMOS) integrated circuits. We designed Penta-CX2 (X = N, P, As, Sb) field-effect transistors (FETs) and utilized first-principles methods to evaluate their quantum transport characteristics. Our results demonstrate that CP2 and CAs2 exhibit superior transport properties and low subthreshold swing (SS) in both n-type and p-type configurations at sub-5 nm channel lengths. For high-performance (HP) applications, the on-state current (Ion) for both n-type and p-type devices exceeds 3000 μA/μm, peaking at 4574 μA/μm. In low-power (LP) applications, Ion for both types of devices surpasses 1000 μA/μm, reaching a maximum of 1735 μA/μm, significantly exceeding the International Roadmap for Devices and Systems (IRDS) standards for HP and LP applications. Furthermore, even when the channel length is reduced to 4 or 3 nm, the devices maintain exceptional performance. Additionally, we established a correlation between carrier effective mass and the saturation current, elucidating how the anisotropy of carrier effective mass influences transport properties and explaining the physical mechanisms by which the device overcomes Boltzmann's tyranny. This study provides valuable insights and references for designing advanced CMOSFETs in the post-Si era using channel materials with unique effective mass.

Monolithic three-dimensional tier-by-tier integration via van der Waals lamination

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1-10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11-13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.

Non-volatile rippled-assisted optoelectronic array for all-day motion detection and recognition

In-sensor processing has the potential to reduce the energy consumption and hardware complexity of motion detection and recognition. However, the state-of-the-art all-in-one array integration technologies with simultaneous broadband spectrum image capture (sensory), image memory (storage) and image processing (computation) functions are still insufficient. Here, macroscale (2 × 2 mm2) integration of a rippled-assisted optoelectronic array (18 × 18 pixels) for all-day motion detection and recognition. The rippled-assisted optoelectronic array exhibits remarkable uniformity in the memory window, optically stimulated non-volatile positive and negative photoconductance. Importantly, the array achieves an extensive optical storage dynamic range exceeding 106, and exceptionally high room-temperature mobility up to 406.7 cm2 V-1 s-1, four times higher than the International Roadmap for Device and Systems 2028 target. Additionally, the spectral range of each rippled-assisted optoelectronic processor covers visible to near-infrared (405 nm-940 nm), achieving function of motion detection and recognition.

The Roadmap of 2D Materials and Devices Toward Chips

Due to the constraints imposed by physical effects and performance degradation, silicon-based chip technology is facing certain limitations in sustaining the advancement of Moore's law. Two-dimensional (2D) materials have emerged as highly promising candidates for the post-Moore era, offering significant potential in domains such as integrated circuits and next-generation computing. Here, in this review, the progress of 2D semiconductors in process engineering and various electronic applications are summarized. A careful introduction of material synthesis, transistor engineering focused on device configuration, dielectric engineering, contact engineering, and material integration are given first. Then 2D transistors for certain electronic applications including digital and analog circuits, heterogeneous integration chips, and sensing circuits are discussed. Moreover, several promising applications (artificial intelligence chips and quantum chips) based on specific mechanism devices are introduced. Finally, the challenges for 2D materials encountered in achieving circuit-level or system-level applications are analyzed, and potential development pathways or roadmaps are further speculated and outlooked.

In Situ Defect Engineering of Controllable Carrier Types in WSe2 for Homomaterial Inverters and Self-Powered Photodetectors

WSe2 has a high mobility of electrons and holes, which is an ideal choice as active channels of electronics in extensive fields. However, carrier-type tunability of WSe2 still has enormous challenges, which are essential to overcome for practical applications. In this work, the direct growth of n-doped few-layer WSe2 is realized via in situ defect engineering. The n-doping of WSe2 is attributed to Se vacancies induced by the H2 flow purged in the cooling process. The electrical measurements based on field effect transistors demonstrate that the carrier type of WSe2 synthesized is successfully transferred from the conventional p-type to the rarely reported n-type. The electron carrier concentration is efficiently modulated by the concentration of H2 during the cooling process. Furthermore, homomaterial inverters and self-powered photodetectors are fabricated based on the doping-type-tunable WSe2. This work reveals a significant way to realize the controllable carrier type of two-dimensional (2D) materials, exhibiting great potential in future 2D electronics engineering.

Integrated Logic Circuits Based on Wafer-Scale 2D-MoS2 FETs Using Buried-Gate Structures

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) materials, such as molybdenum disulfide (MoS2), stand out due to their atomically thin layered structure and exceptional electrical properties. Consequently, they could potentially become one of the main materials for future integrated high-performance logic circuits. However, the local back-gate-based MoS2 transistors on a silicon substrate can lead to the degradation of electrical characteristics. This degradation is caused by the abnormal effect of gate sidewalls, leading to non-uniform field controllability. Therefore, the buried-gate-based MoS2 transistors where the gate electrodes are embedded into the silicon substrate are fabricated. The several device parameters such as field-effect mobility, on/off current ratio, and breakdown voltage of gate dielectric are dramatically enhanced by field-effect mobility (from 0.166 to 1.08 cm2/V·s), on/off current ratio (from 4.90 × 105 to 1.52 × 107), and breakdown voltage (from 15.73 to 27.48 V) compared with a local back-gate-based MoS2 transistor, respectively. Integrated logic circuits, including inverters, NAND, NOR, AND, and OR gates, were successfully fabricated by 2-inch wafer-scale through the integration of a buried-gate MoS2 transistor array.

Electrical Contacts With 2D Materials: Current Developments and Future Prospects

Current electrical contact models are occasionally insufficient at the nanoscale owing to the wide variations in outcomes between 2D mono and multi-layered and bulk materials that result from their distinctive electrostatics and geometries. Contrarily, devices based on 2D semiconductors present a significant challenge due to the requirement for electrical contact with resistances close to the quantum limit. The next generation of low-power devices is already hindered by the lack of high-quality and low-contact-resistance contacts on 2D materials. The physics and materials science of electrical contact resistance in 2D materials-based nanoelectronics, interface configurations, charge injection mechanisms, and numerical modeling of electrical contacts, as well as the most pressing issues that need to be resolved in the field of research and development, will all be covered in this review.