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For: Pandey CK, Singh A, Chaudhury S. Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances. Appl Phys A 2020;126:225. [DOI: 10.1007/s00339-020-3402-2] [Citation(s) in RCA: 1] [Impact Index Per Article: 0.3] [Reference Citation Analysis] [What about the content of this article? (0)] [Track Full Text] [Subscribe] [Scholar Register] [Received: 09/23/2019] [Accepted: 02/11/2020] [Indexed: 07/19/2023]

For:	Pandey CK, Singh A, Chaudhury S. Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances. Appl Phys A 2020;126:225. [DOI: 10.1007/s00339-020-3402-2] [Citation(s) in RCA: 1] [Impact Index Per Article: 0.3] [Reference Citation Analysis] [What about the content of this article? (0)] [Track Full Text] [Subscribe] [Scholar Register] [Received: 09/23/2019] [Accepted: 02/11/2020] [Indexed: 07/19/2023]

Number	Cited by Other Article(s)
1	Pandey CK, Singh A, Chaudhury S. A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET. MICROELECTRONICS RELIABILITY 2021;122:114166. [DOI: 10.1016/j.microrel.2021.114166] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 07/19/2023] Abstract Collapse Key Words Collapse MESH Headings Collapse Grants Collapse Affiliation(s) Collapse

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Cited by Other Article(s)

Pandey CK, Singh A, Chaudhury S. A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET. MICROELECTRONICS RELIABILITY 2021;122:114166. [DOI: 10.1016/j.microrel.2021.114166] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 07/19/2023]