STBNN: Hardware-friendly spatio-temporal binary neural network with high pattern recognition accuracy

A low cost neuromorphic learning engine based on a high performance supervised SNN learning algorithm

Spiking neural networks (SNNs) are more energy- and resource-efficient than artificial neural networks (ANNs). However, supervised SNN learning is a challenging task due to non-differentiability of spikes and computation of complex terms. Moreover, the design of SNN learning engines is not an easy task due to limited hardware resources and tight energy constraints. In this article, a novel hardware-efficient SNN back-propagation scheme that offers fast convergence is proposed. The learning scheme does not require any complex operation such as error normalization and weight-threshold balancing, and can achieve an accuracy of around 97.5% on MNIST dataset using only 158,800 synapses. The multiplier-less inference engine trained using the proposed hard sigmoid SNN training (HaSiST) scheme can operate at a frequency of 135 MHz and consumes only 1.03 slice registers per synapse, 2.8 slice look-up tables, and can infer about 0.03[Formula: see text] features in a second, equivalent to 9.44 giga synaptic operations per second (GSOPS). The article also presents a high-speed, cost-efficient SNN training engine that consumes only 2.63 slice registers per synapse, 37.84 slice look-up tables per synapse, and can operate at a maximum computational frequency of around 50 MHz on a Virtex 6 FPGA.

S3NN: Time step reduction of spiking surrogate gradients for training energy efficient single-step spiking neural networks

As the scales of neural networks increase, techniques that enable them to run with low computational cost and energy efficiency are required. From such demands, various efficient neural network paradigms, such as spiking neural networks (SNNs) or binary neural networks (BNNs), have been proposed. However, they have sticky drawbacks, such as degraded inference accuracy and latency. To solve these problems, we propose a single-step spiking neural network (S³NN), an energy-efficient neural network with low computational cost and high precision. The proposed S³NN processes the information between hidden layers by spikes as SNNs. Nevertheless, it has no temporal dimension so that there is no latency within training and inference phases as BNNs. Thus, the proposed S³NN has a lower computational cost than SNNs that require time-series processing. However, S³NN cannot adopt naïve backpropagation algorithms due to the non-differentiability nature of spikes. We deduce a suitable neuron model by reducing the surrogate gradient for multi-time step SNNs to a single-time step. We experimentally demonstrated that the obtained surrogate gradient allows S³NN to be trained appropriately. We also showed that the proposed S³NN could achieve comparable accuracy to full-precision networks while being highly energy-efficient.

Efficient Binary Weight Convolutional Network Accelerator for Speech Recognition

Speech recognition has progressed tremendously in the area of artificial intelligence (AI). However, the performance of the real-time offline Chinese speech recognition neural network accelerator for edge AI needs to be improved. This paper proposes a configurable convolutional neural network accelerator based on a lightweight speech recognition model, which can dramatically reduce hardware resource consumption while guaranteeing an acceptable error rate. For convolutional layers, the weights are binarized to reduce the number of model parameters and improve computational and storage efficiency. A multichannel shared computation (MCSC) architecture is proposed to maximize the reuse of weight and feature map data. The binary weight-sharing processing engine (PE) is designed to avoid limiting the number of multipliers. A custom instruction set is established according to the variable length of voice input to configure parameters for adapting to different network structures. Finally, the ping-pong storage method is used when the feature map is an input. We implemented this accelerator on Xilinx ZYNQ XC7Z035 under the working frequency of 150 MHz. The processing time for 2.24 s and 8 s of speech was 69.8 ms and 189.51 ms, respectively, and the convolution performance reached 35.66 GOPS/W. Compared with other computing platforms, accelerators perform better in terms of energy efficiency, power consumption and hardware resource consumption.

A Co-Designed Neuromorphic Chip With Compact (17.9K F2) and Weak Neuron Number-Dependent Neuron/Synapse Modules

Many efforts have been made to improve the neuron integration efficiency on neuromorphic chips, such as using emerging memory devices and shrinking CMOS technology nodes. However, in the fully connected (FC) neuromorphic core, increasing the number of neurons will lead to a square increase in synapse & dendrite costs and a high-slope linear increase in soma costs, resulting in an explosive growth of core hardware costs. We propose a co-designed neuromorphic core (SRCcore) based on the quantized spiking neural network (SNN) technology and compact chip design methodology. The cost of the neuron/synapse module in SRCcore weakly depends on the neuron number, which effectively relieves the growth pressure of the core area caused by increasing the neuron number. In the proposed BICS chip based on SRCcore, although the neuron/synapse module implements 1∼16 times of neurons and 1∼66 times of synapses, it only costs an area of 1.79 × 10⁷ F², which is 7.9%∼38.6% of that in previous works. Based on the weight quantization strategy matched with SRCcore, quantized SNNs achieve 0.05%∼2.19% higher accuracy than previous works, thus supporting the design and application of SRCcore. Finally, a cross-modeling application is demonstrated based on the chip. We hope this work will accelerate the development of cortical-scale neuromorphic systems.