Small-Signal Performance and Modeling of sub-50nm nMOSFETs with f above 460-GHz

RC-Effects on the Oxide of SOI MOSFET under Off-State TDDB Degradation: RF Characterization and Modeling

Based on S-parameter measurements, the effect of dynamic trapping and de-trapping of charge in the gate oxide, the increase of dielectric loss due to polarization, and the impact of leakage current on the small-signal input impedance at RF is analyzed and represented. This is achieved by systematically extracting the corresponding model parameters from single device measurements at different frequency ranges, and then the methodology is applied to analyze the evolution of these parameters when the device is submitted to non-conducting electrical stress. This approach not only allows to inspect the impact of effects not occurring under DC conditions, such as the current due to the time varying dielectric polarization, but also to clearly distinguish effects in accordance with the functional form of their contribution to the device's impedance. In fact, it is shown that minor changes in the model of the gate capacitance by including additional resistive and capacitive components allows for an excellent model-experiment correlation up to 30 GHz. Moreover, the accuracy of the correlation is shown to be maintained when applying the proposal to the device under different gate-to-source bias conditions and at several stages during off-state degradation.

A Multi-Output Multi-String High-Efficiency WLED Driver Using 40 nm CMOS Technology

In this work, a multi-independent-output, multi-string, high-efficiency, boost-converter-based white LED (WLED) driver architecture is proposed. It utilizes a single inductor main switch with a common maximum duty cycle controller (MDCC) in the feedback loop. A simple pulse skipping controller (PSC) is utilized in each high-side switch of the multiple independent outputs. Despite the presence of multiple independent outputs, a single over-voltage protection (OVP) circuit is used at the output to protect the circuit from any voltage above 27 V. An open circuit in any of the strings is addressed, in addition to the LED’s short-circuit conditions. Excellent current matching between strings is achieved, despite the low ON-resistance (Rdson) of transistors used in the 40 nm process. Most circuits are designed in digital CMOS logic to overcome the extreme process variations in the 40 nm node. Compared to a single output parallel strings topology, a 50% improvement in efficiency is achieved relative to extremely unbalanced strings. Three strings are used in this proposal, but more strings can be supported with the same topology. Each string is driven by a 25 mA current sink. An input voltage of 3.2–4.2 V and an output voltage up to 27 V are supported.

Nanotube electronics for radiofrequency applications

Electronic devices based on carbon nanotubes are among the candidates to eventually replace silicon-based devices for logic applications. Before then, however, nanotube-based radiofrequency transistors could become competitive for high-performance analogue components such as low-noise amplifiers and power amplifiers in wireless systems. Single-walled nanotubes are well suited for use in radiofrequency transistors because they demonstrate near-ballistic electron transport and are expected to have high cut-off frequencies. To achieve the best possible performance it is necessary to use dense arrays of semiconducting nanotubes with good alignment between the nanotubes, but techniques that can economically manufacture such arrays are needed to realize this potential. Here we review progress towards nanotube electronics for radiofrequency applications in terms of device physics, circuit design and the manufacturing challenges.