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Zhang Z, Tang W, Chen J, Zhang Y, Zhang C, Fu M, Huang F, Li X, Zhang C, Wu Z, Wu Y, Kang J. Manipulations of Electronic and Spin States in Co-Quantum Dot/WS 2 Heterostructure on a Metal-Dielectric Composite Substrate by Controlling Interfacial Carriers. Nano Lett 2024; 24:1415-1422. [PMID: 38232178 DOI: 10.1021/acs.nanolett.3c04831] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 01/19/2024]
Abstract
Charge and spin are two intrinsic attributes of carriers governing almost all of the physical processes and operation principles in materials. Here, we demonstrate the manipulation of electronic and spin states in designed Co-quantum dot/WS2 (Co-QDs/WS2) heterostructures by employing a metal-dielectric composite substrate and via scanning tunneling microscope. By repeatedly scanning under a unipolar bias, switching the bias polarity, or applying a pulse through nonmagnetic or magnetic tips, the Co-QDs morphologies exhibit a regular and reproducible transformation between bright and dark dots. First-principles calculations reveal that these tunable characters are attributed to the variation of density of states and the transition of magnetic anisotropy energy induced by carrier accumulation. It also suggests that the metal-dielectric composite substrate is successful in creating the interfacial potential for carrier accumulation and realizes the electrically controllable modulations. These results will promote the exploration of electron-matter interactions in quantum systems and provide an innovative way to facilitate the development of spintronics.
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Affiliation(s)
- Zongnan Zhang
- Department of Physics, Engineering Research Centre for Micro-Nano Optoelectronic Materials and Devices at Education Ministry, Fujian Provincial Key Laboratory of Semiconductor Materials and Applications, Xiamen University, Xiamen 361005, People's Republic of China
| | - Weiqing Tang
- Gusu Laboratory of Materials, Suzhou 215000, Jiangsu, People's Republic of China
| | - Jiajun Chen
- Department of Physics, Engineering Research Centre for Micro-Nano Optoelectronic Materials and Devices at Education Ministry, Fujian Provincial Key Laboratory of Semiconductor Materials and Applications, Xiamen University, Xiamen 361005, People's Republic of China
| | - Yuxiang Zhang
- Department of Physics, Engineering Research Centre for Micro-Nano Optoelectronic Materials and Devices at Education Ministry, Fujian Provincial Key Laboratory of Semiconductor Materials and Applications, Xiamen University, Xiamen 361005, People's Republic of China
| | - Chenhao Zhang
- Department of Physics, Engineering Research Centre for Micro-Nano Optoelectronic Materials and Devices at Education Ministry, Fujian Provincial Key Laboratory of Semiconductor Materials and Applications, Xiamen University, Xiamen 361005, People's Republic of China
| | - Mingming Fu
- Department of Physics, Engineering Research Centre for Micro-Nano Optoelectronic Materials and Devices at Education Ministry, Fujian Provincial Key Laboratory of Semiconductor Materials and Applications, Xiamen University, Xiamen 361005, People's Republic of China
| | - Feihong Huang
- Department of Physics, Engineering Research Centre for Micro-Nano Optoelectronic Materials and Devices at Education Ministry, Fujian Provincial Key Laboratory of Semiconductor Materials and Applications, Xiamen University, Xiamen 361005, People's Republic of China
| | - Xu Li
- Department of Physics, Engineering Research Centre for Micro-Nano Optoelectronic Materials and Devices at Education Ministry, Fujian Provincial Key Laboratory of Semiconductor Materials and Applications, Xiamen University, Xiamen 361005, People's Republic of China
| | - Chunmiao Zhang
- Department of Physics, Engineering Research Centre for Micro-Nano Optoelectronic Materials and Devices at Education Ministry, Fujian Provincial Key Laboratory of Semiconductor Materials and Applications, Xiamen University, Xiamen 361005, People's Republic of China
| | - Zhiming Wu
- Department of Physics, Engineering Research Centre for Micro-Nano Optoelectronic Materials and Devices at Education Ministry, Fujian Provincial Key Laboratory of Semiconductor Materials and Applications, Xiamen University, Xiamen 361005, People's Republic of China
| | - Yaping Wu
- Department of Physics, Engineering Research Centre for Micro-Nano Optoelectronic Materials and Devices at Education Ministry, Fujian Provincial Key Laboratory of Semiconductor Materials and Applications, Xiamen University, Xiamen 361005, People's Republic of China
| | - Junyong Kang
- Department of Physics, Engineering Research Centre for Micro-Nano Optoelectronic Materials and Devices at Education Ministry, Fujian Provincial Key Laboratory of Semiconductor Materials and Applications, Xiamen University, Xiamen 361005, People's Republic of China
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Meyer M, Déprez C, Meijer IN, Unseld FK, Karwal S, Sammak A, Scappucci G, Vandersypen LMK, Veldhorst M. Single-Electron Occupation in Quantum Dot Arrays at Selectable Plunger Gate Voltage. Nano Lett 2023; 23:11593-11600. [PMID: 38091376 PMCID: PMC10755753 DOI: 10.1021/acs.nanolett.3c03349] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Key Words] [Grants] [Track Full Text] [Subscribe] [Scholar Register] [Received: 09/03/2023] [Revised: 12/06/2023] [Accepted: 12/07/2023] [Indexed: 12/28/2023]
Abstract
The small footprint of semiconductor qubits is favorable for scalable quantum computing. However, their size also makes them sensitive to their local environment and variations in the gate structure. Currently, each device requires tailored gate voltages to confine a single charge per quantum dot, clearly challenging scalability. Here, we tune these gate voltages and equalize them solely through the temporary application of stress voltages. In a double quantum dot, we reach a stable (1,1) charge state at identical and predetermined plunger gate voltage and for various interdot couplings. Applying our findings, we tune a 2 × 2 quadruple quantum dot such that the (1,1,1,1) charge state is reached when all plunger gates are set to 1 V. The ability to define required gate voltages may relax requirements on control electronics and operations for spin qubit devices, providing means to advance quantum hardware.
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Affiliation(s)
- Marcel Meyer
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The
Netherlands
| | - Corentin Déprez
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The
Netherlands
| | - Ilja N. Meijer
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The
Netherlands
| | - Florian K. Unseld
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The
Netherlands
| | - Saurabh Karwal
- QuTech
and Netherlands Organisation for Applied Scientific Research (TNO), PO Box 155, 2600 AD Delft, The Netherlands
| | - Amir Sammak
- QuTech
and Netherlands Organisation for Applied Scientific Research (TNO), PO Box 155, 2600 AD Delft, The Netherlands
| | - Giordano Scappucci
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The
Netherlands
| | - Lieven M. K. Vandersypen
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The
Netherlands
| | - Menno Veldhorst
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The
Netherlands
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Kong Z, Song Y, Wang H, Liu X, Wang X, Liu J, Li B, Su J, Tan X, Luan Q, Lin H, Ren Y, Zhang Y, Liu J, Li J, Du A, Radamson HH, Zhao C, Ye T, Wang G. Interface Investigation on SiGe/Si Multilayer Structures: Influence of Different Epitaxial Process Conditions. ACS Appl Mater Interfaces 2023; 15:56567-56574. [PMID: 37988059 DOI: 10.1021/acsami.3c14168] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 11/22/2023]
Abstract
SiGe/Si multilayer is the core structure of the active area of gate-all-around field-effect transistors and semiconductor quantum computing devices. In this paper, high-quality SiGe/Si multilayers have been grown by a reduced-pressure chemical vapor deposition system. The effects of temperature, pressure, interface processing (dichlorosilane (SiH2Cl2, DCS) and hydrogen chloride (HCl)) on improving the transition thickness of SiGe to Si interfaces were investigated. The interface quality was characterized by transmission electron microscopy/atomic force microscopy/high-resolution X-ray diffraction methods. It was observed that limiting the migration of Ge atoms in the interface was critical for optimizing a sharp interface, and the addition of DCS was found to decrease the interface transition thickness. The change of the interfacial transition layer is not significant in the short treatment time of HCl. When the processing time of HCl is increased, the internal interface is optimized to a certain extent but the corresponding film thickness is also reduced. This study provides technical support for the acquisition of an abrupt interface and will have a very favorable influence on the performance improvement of miniaturized devices in the future.
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Affiliation(s)
- Zhenzhen Kong
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, P. R. China
- Microelectronics Institute, University of Chinese Academy of Sciences, Beijing 100049, P. R. China
| | - Yanpeng Song
- Beijing Superstring Academy of Memory Technology, Beijing 100176, P. R. China
| | - Hailing Wang
- Beijing Superstring Academy of Memory Technology, Beijing 100176, P. R. China
| | - Xiaomeng Liu
- Beijing Superstring Academy of Memory Technology, Beijing 100176, P. R. China
| | - Xiangsheng Wang
- Beijing Superstring Academy of Memory Technology, Beijing 100176, P. R. China
| | - Jinbiao Liu
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, P. R. China
- Microelectronics Institute, University of Chinese Academy of Sciences, Beijing 100049, P. R. China
| | - Ben Li
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangdong 510535, P. R. China
| | - Jiale Su
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, P. R. China
| | - Xinguang Tan
- Beijing Superstring Academy of Memory Technology, Beijing 100176, P. R. China
| | - Qingjie Luan
- Beijing Superstring Academy of Memory Technology, Beijing 100176, P. R. China
| | - Hongxiao Lin
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangdong 510535, P. R. China
| | - Yuhui Ren
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, P. R. China
- Microelectronics Institute, University of Chinese Academy of Sciences, Beijing 100049, P. R. China
| | - Yiwen Zhang
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, P. R. China
- Microelectronics Institute, University of Chinese Academy of Sciences, Beijing 100049, P. R. China
| | - Jingxiong Liu
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, P. R. China
- Microelectronics Institute, University of Chinese Academy of Sciences, Beijing 100049, P. R. China
| | - Junfeng Li
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, P. R. China
| | - Anyan Du
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, P. R. China
| | - Henry H Radamson
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangdong 510535, P. R. China
| | - Chao Zhao
- Beijing Superstring Academy of Memory Technology, Beijing 100176, P. R. China
| | - Tianchun Ye
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, P. R. China
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangdong 510535, P. R. China
| | - Guilei Wang
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, P. R. China
- Beijing Superstring Academy of Memory Technology, Beijing 100176, P. R. China
- Hefei National Laboratory, University of Science and Technology of China, Hefei, Anhui 230088, P. R. China
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4
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Varley JB, Ray KG, Lordi V. Dangling Bonds as Possible Contributors to Charge Noise in Silicon and Silicon-Germanium Quantum Dot Qubits. ACS Appl Mater Interfaces 2023; 15:43111-43123. [PMID: 37651689 DOI: 10.1021/acsami.3c06725] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 09/02/2023]
Abstract
Spin qubits based on Si and Si1-xGex quantum dot architectures exhibit among the best coherence times of competing quantum computing technologies, yet they still suffer from charge noise that limit their qubit gate fidelities. Identifying the origins of these charge fluctuations is therefore a critical step toward improving Si quantum-dot-based qubits. Here, we use hybrid functional calculations to investigate possible atomistic sources of charge noise, focusing on charge trapping at Si and Ge dangling bonds (DBs). We evaluate the role of global and local environment in the defect levels associated with DBs in Si, Ge, and Si1-xGex alloys, and consider their trapping and excitation energies within the framework of configuration coordinate diagrams. We additionally consider the influence of strain and oxidation in charge-trapping energetics by analyzing Si and GeSi DBs in SiO2 and strained Si layers in typical Si1-xGex quantum dot heterostructures. Our results identify that Ge dangling bonds are more problematic charge-trapping centers both in typical Si1-xGex alloys and associated oxidation layers, and they may be exacerbated by compositional inhomogeneities. These results suggest the importance of alloy homogeneity and possible passivation schemes for DBs in Si-based quantum dot qubits and are of general relevance to mitigating possible trap levels in other Si, Ge, and Si1-xGex-based metal-oxide-semiconductor stacks and related devices.
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Affiliation(s)
- Joel B Varley
- Materials Science Division, Lawrence Livermore National Laboratory, Livermore, California 94550, United States
| | - Keith G Ray
- Materials Science Division, Lawrence Livermore National Laboratory, Livermore, California 94550, United States
| | - Vincenzo Lordi
- Materials Science Division, Lawrence Livermore National Laboratory, Livermore, California 94550, United States
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Meyer M, Déprez C, van Abswoude TR, Meijer IN, Liu D, Wang CA, Karwal S, Oosterhout S, Borsoi F, Sammak A, Hendrickx NW, Scappucci G, Veldhorst M. Electrical Control of Uniformity in Quantum Dot Devices. Nano Lett 2023; 23:2522-2529. [PMID: 36975126 PMCID: PMC10103318 DOI: 10.1021/acs.nanolett.2c04446] [Citation(s) in RCA: 5] [Impact Index Per Article: 5.0] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Key Words] [Grants] [Track Full Text] [Figures] [Subscribe] [Scholar Register] [Received: 11/11/2022] [Revised: 03/20/2023] [Indexed: 06/18/2023]
Abstract
Highly uniform quantum systems are essential for the practical implementation of scalable quantum processors. While quantum dot spin qubits based on semiconductor technology are a promising platform for large-scale quantum computing, their small size makes them particularly sensitive to their local environment. Here, we present a method to electrically obtain a high degree of uniformity in the intrinsic potential landscape using hysteretic shifts of the gate voltage characteristics. We demonstrate the tuning of pinch-off voltages in quantum dot devices over hundreds of millivolts that then remain stable at least for hours. Applying our method, we homogenize the pinch-off voltages of the plunger gates in a linear array for four quantum dots, reducing the spread in pinch-off voltages by one order of magnitude. This work provides a new tool for the tuning of quantum dot devices and offers new perspectives for the implementation of scalable spin qubit arrays.
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Affiliation(s)
- Marcel Meyer
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
| | - Corentin Déprez
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
| | - Timo R. van Abswoude
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
| | - Ilja N. Meijer
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
| | - Dingshan Liu
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
| | - Chien-An Wang
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
| | - Saurabh Karwal
- QuTech
and Netherlands Organisation for Applied Scientific Research (TNO), PO Box 155, 2600 AD Delft, The Netherlands
| | - Stefan Oosterhout
- QuTech
and Netherlands Organisation for Applied Scientific Research (TNO), PO Box 155, 2600 AD Delft, The Netherlands
| | - Francesco Borsoi
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
| | - Amir Sammak
- QuTech
and Netherlands Organisation for Applied Scientific Research (TNO), PO Box 155, 2600 AD Delft, The Netherlands
| | - Nico W. Hendrickx
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
| | - Giordano Scappucci
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
| | - Menno Veldhorst
- QuTech
and Kavli Institute of Nanoscience, Delft
University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
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