Physical Properties of an Ultrathin Al2O3/HfO2 Composite Film by Atomic Layer Deposition and the Application in Thin-Film Transistors

Interfacial modulation and optimization of the electrical properties of ZrGdO x composite films prepared using a UVO-assisted sol-gel method

In this paper, Gd-doped ZrO2 gate dielectric films and metal-oxide-semiconductor (MOS) capacitors structured as Al/ZrGdO x /Si were prepared using an ultraviolet ozone (UVO)-assisted sol-gel method. The effects of heat treatment temperature on the microstructure, chemical bonding state, optical properties, surface morphology and electrical characteristics of the ZrGdO x composite films and MOS capacitors were systematically investigated. The crystalline phase of the ZrGdO x films appeared only at 600 °C, indicating that Gd doping effectively inhibits the crystallization of ZrO2 films. Meanwhile, as the heat treatment temperature increased from 300 °C to 600 °C, the content of oxygen vacancies decreased from 18.57% to 11.95%, and the content of metal-hydroxyl-oxygen bonds decreased from 14.72% to 8.64%. Heat treatment temperature proved to be effective in passivating the oxygen defects and reducing the trap density within the dielectric layer. At 500 °C, the MOS capacitor exhibited the best electrical characteristics, including the highest dielectric constant (k = 19.3), the smallest hysteresis (ΔV fb = 0.01 V), the lowest boundary trapping oxide charge density (N bt = 2.7 × 1010 cm-2), and the lowest leakage current density (J = 9.61 × 10-6 A cm-2). Therefore, adjusting the heat treatment temperature can significantly improve the performance of ZrGdO x composite films and capacitors, which is favorable for the application of CMOS devices in large-scale and high-performance electronic systems.

Chemistry Informed Machine Learning-Based Heat Capacity Prediction of Solid Mixed Oxides

Knowing heat capacity is crucial for modeling temperature changes with the absorption and release of heat and for calculating the thermal energy storage capacity of oxide mixtures with energy applications. The current prediction methods (ab initio simulations, computational thermodynamics, and the Neumann-Kopp rule) are computationally expensive, not fully generalizable, or inaccurate. Machine learning has the potential of being fast, accurate, and generalizable, but it has been scarcely used to predict mixture properties, particularly for mixed oxides. Here, we demonstrate a method for the generalizable prediction of heat capacity of solid oxide pseudobinary mixtures using heat capacity data obtained from computational thermodynamics and descriptors from ab initio databases. Models trained through this workflow achieved an error (mean absolute error of 0.43 J mol-1 K-1) lower than the uncertainty in differential scanning calorimetry measurements, and the workflow can be extended to predict other properties derived from the Gibbs free energy and for higher-order oxide mixtures.

Steep-slope vertical-transport transistors built from sub-5 nm Thin van der Waals heterostructures

Two-dimensional (2D) semiconductor-based vertical-transport field-effect transistors (VTFETs) - in which the current flows perpendicularly to the substrate surface direction - are in the drive to surmount the stringent downscaling constraints faced by the conventional planar FETs. However, low-power device operation with a sub-60 mV/dec subthreshold swing (SS) at room temperature along with an ultra-scaled channel length remains challenging for 2D semiconductor-based VTFETs. Here, we report steep-slope VTFETs that combine a gate-controllable van der Waals heterojunction and a metal-filamentary threshold switch (TS), featuring a vertical transport channel thinner than 5 nm and sub-thermionic turn-on characteristics. The integrated TS-VTFETs were realised with efficient current switching behaviours, exhibiting a current modulation ratio exceeding 1 × 108 and an average sub-60 mV/dec SS over 6 decades of drain current. The proposed TS-VTFETs with excellent area- and energy-efficiency could help to tackle the performance degradation-device downscaling dilemma faced by logic transistor technologies.