Gigahertz Field-Effect Transistors with CMOS-Compatible Transfer-Free Graphene

Unveiling the impact of the bias-dependent charge neutrality point on graphene based multi-transistor applications

The Dirac voltage of a graphene field-effect transistor (GFET) stands for the gate bias that sets the charge neutrality condition in the channel, thus resulting in a minimum conductivity. Controlling its dependence on the terminal biases is crucial for the design and optimization of radio-frequency applications based on multiple GFETs. However, the previous analysis of such dependence carried out for single devices is uncomplete and if not properly understood could result in circuit designs with poor performance. The control of the Dirac point shift (DPS) is particularly important for the deployment of graphene-based differential circuit topologies where keeping a strict symmetry between the electrically balanced branches is essential for exploiting the advantages of such topologies. This note sheds light on the impact of terminal biases on the DPS in a real device and sets a rigorous methodology to control it so to eventually optimize and exploit the performance of radio-frequency applications based on GFETs.

Polymer-assisted TEM specimen preparation method for oxidation-sensitive 2D materials

By structural and analytical TEM and scanning electron microscopy experiments we show that atomically-resolved structural characterization of oxidation-sensitive two-dimensional material is strongly hindered when the final step of the preparation process, the transfer to the TEM grid, is performed with a wet etching method involving bases or acids, interacting with the highly reactive sample surface. Here we present an alternative polymer-assisted and mechanical-exfoliation-based sample preparation method and demonstrate it on selected oxidation-sensitive transition metal phosphorus trisulfides and transition metal dichalcogenides. The analysis, obtained from the samples prepared with both of the methods clearly show that oxidation is the origin of discrepancy, the oxidation during the final preparation step is strongly reduced only when the new method is applied, and atomically-resolved structural characterization of the pristine structures is now possible.

Graphene-Transition Metal Dichalcogenide Heterojunctions for Scalable and Low-Power Complementary Integrated Circuits

The most pressing barrier for the development of advanced electronics based on two-dimensional (2D) layered semiconductors stems from the lack of site-selective synthesis of complementary n- and p-channels with low contact resistance. Here, we report an in-plane epitaxial route for the growth of interlaced 2D semiconductor monolayers using chemical vapor deposition with a gas-confined scheme, in which patterned graphene (Gr) serves as a guiding template for site-selective growth of Gr-WS₂-Gr and Gr-WSe₂-Gr heterostructures. The Gr/2D semiconductor interface exhibits a transparent contact with a nearly ideal pinning factor of 0.95 for the n-channel WS₂ and 0.92 for the p-channel WSe₂. The effective depinning of the Fermi level gives an ultralow contact resistance of 0.75 and 1.20 kΩ·μm for WS₂ and WSe₂, respectively. Integrated logic circuits including inverter, NAND gate, static random access memory, and five-stage ring oscillator are constructed using the complementary Gr-WS₂-Gr-WSe₂-Gr heterojunctions as a fundamental building block, featuring the prominent performance metrics of high operation frequency (>0.2 GHz), low-power consumption, large noise margins, and high operational stability. The technology presented here provides a speculative look at the electronic circuitry built on atomic-scale semiconductors in the near future.

High-Mobility InSe Transistors: The Nature of Charge Transport

InSe is a high-mobility layered semiconductor with mobility being highly sensitive to any surrounding media that could act as a source of extrinsic scattering. However, little effort has been made to understand electronic transport in thin InSe layers with native surface oxide formed spontaneously upon exposure to an ambient environment. Here, we explore the influence of InO_x/InSe interfacial trap states on electronic transport in thin InSe layers. We show that wet oxidation (processed in an ambient environment) causes massive deep-lying band-tail states, through which electrons conduct via 2D variable-range hopping with a short localization length of 1-3 nm. In contrast, a high-quality InO_x/InSe interface can be formed in dry oxidation (processed in pure oxygen), with a low trap density of 10¹² eV^-1 cm^-2. Metal-insulator transition can be thus observed in the gate sweep of the field-effect transistors (FETs), indicative of band transport predominated by extended states above the mobility edge. A room-temperature band mobility of 10³ cm²/V s is obtained. The profound difference in the transport behavior between the wet and dry InSe FETs suggests that fluctuating Coulomb potential arising from trapped charges at the InO_x/InSe interface is the dominant source of disorders in thin InSe channels.

Ultrafast Monolayer In/Gr-WS2-Gr Hybrid Photodetectors with High Gain

One of the primary limitations of previously reported two-dimensional (2D) photodetectors is a low frequency response (≪ 1 Hz) for sensitive devices with gain. Yet, little efforts have been devoted to improve the temporal response of photodetectors while maintaining high gain and responsivity. Here, we demonstrate a gain of 6.3 × 10³ electrons per photon and a responsivity of 2.6 × 10³ A/W while simultaneously exhibiting an ultrafast response time of 40-65 μs in a hybrid photodetector that consists of graphene-WS₂-graphene junctions covered with indium (In) adatoms atop. The resultant responsivity is 6 orders of magnitude higher than that of conventional photodetectors comprising solely of a Au-WS₂-Au junction. The photogain is provided mainly by the adsorbed In adatoms, from which photogenerated electrons can be transferred to the WS₂ channel, while holes remain trapped in In adatoms, leading to a photogating effect as electrons are recirculating during the residence of holes in In adatoms. At a gate voltage near the Dirac point of graphene, a detectivity of D* = 2.2 × 10¹² Jones and an ON/OFF ratio of 10⁴ are achieved. The enhanced performance of the device can be attributed partly to the transparent graphene/WS₂ contact and partly to the strong capacitive coupling of the In adatoms with the WS₂ channel, which enables ultrafast carrier dynamics.