Symmetric Ambipolar Thin-Film Transistors and High-Gain CMOS-like Inverters Using Environmentally Friendly Copper Nitride

Enhancement-Mode Ambipolar Thin-Film Transistors and CMOS Logic Circuits using Bilayer Ga2O3/NiO Semiconductors

Recent advancements in power electronics have been driven by Ga2O3-based ultrawide bandgap (UWBG) semiconductor devices, enabling efficient high-current switching. However, integrating Ga2O3 power devices with essential silicon CMOS logic circuits for advanced control poses fabrication challenges. Researchers have introduced Ga2O3-based NMOS and pseudo-CMOS circuits for integration, but these circuits may either consume more power or increase the design complexity. Hence, this article proposes Ga2O3-based CMOS realized using heterogeneous 3D-stacked bilayer ambipolar transistors. These ambipolar transistors consist of HfO2/NiO/Ga2O3/NiO/HfO2 heterostructures that are wrapped around by the Ti/Au gate electrode, resulting in record high electron and hole current on/off ratios of 109 and 107. The threshold voltage, subthreshold swing, and current density measured from 100 ambipolar devices (across 5 batches) are around -7.99 ± 0.92 V (p-channel) and 7.81 ± 0.81 V (n-channel), 0.59 ± 0.07 V/dec (p-channel) and 0.61 ± 0.06 V/dec (n-channel), and 0.99 ± 0.26 mA/mm (p-channel) and 58.23 ± 12.99 mA/mm (n-channel), respectively. All the 100 ambipolar devices showed decent long-term stability over a period of 200 days, exhibiting reliable electrical performance. The threshold voltage shift (ΔVTH) after negative bias stressing for a period of 3500 s is around 11.52 V (p-channel) and 10.21 V (n-channel), respectively. Notably, the n-channels exhibit ∼2 orders higher on/off ratio than the best Ga2O3 unipolar transistors at 300 °C. Moreover, the polarities of ambipolar transistors are reconfigurable into p- or n-MOS, which are integrated to demonstrate CMOS inverter, NOR, and NAND logic gates. The switching periods from "0" to "1" and from "1" to "0" of NOR are 0.12 and 0.17 μs, and those of NAND are 0.16 and 0.13 μs. This work lays the foundation of oxide-semiconductor-based CMOS for future integrated electronics.

Hole-Doping to a Cu(I)-Based Semiconductor with an Isovalent Cation: Utilizing a Complex Defect as a Shallow Acceptor

p-Type doping in Cu(I)-based semiconductors is pivotal for solar cell photoabsorbers and hole transport materials to improve the device performance. Impurity doping is a fundamental technology to overcome the intrinsic limits of hole concentration controlled by native defects. Here, we report that alkali metal impurities are prominent p-type dopants for the Cu(I)-based cation-deficient hole conductors. When the size mismatch with Cu⁺ in the host lattice is increased, these isovalent impurities are preferentially located at interstitial positions to interact with the constituent Cu cations, forming stable impurity-defect complexes. We demonstrate that the Cs impurity in γ-CuI semiconductors enhances hole concentration controllability for single crystals and thin films in the range of 10¹³-10¹⁹ cm^-3. First-principles calculations indicate that the Cs impurity forms impurity-defect complexes that act as shallow acceptors leading to the increased p-type conductivity. This isovalent doping provides an approach for controlled doping into cation-deficient semiconductors through an interaction of impurities with native defects.