Low delay rate adaptive pacemaker using FPGA embedded piezoelectric sensor

Design and Implementation of a Sense Amplifier for Low-Power Cardiac Pacemaker

This paper presents the implementation of a sense amplifier for a low-power cardiac pacemaker using the Differential Voltage Current Conveyor (DVCC). Two significant aspects of the pacemaker are sensing and pacing. The pulse generator, which is the heart of the pacemaker, consists of a sense amplifier, a logic unit and a timing control unit. The sense amplifier comprises an instrumentation amplifier, a bandpass filter and a comparator that are used to detect the QRS complex wave from the cardiac signal. Based on the output of a sense amplifier, the logic unit and the timing control unit decide whether to pace the heart or not, which achieves the requirement of the demand pacing. In this paper, a novel design of the sense amplifier using a DVCC is proposed, and the simulations are performed using 130-nm TSMC technology. Furthermore, the modes of the pacemaker VVI, DDD and rate-responsive algorithms have been implemented using the structural approach in VHDL by taking into consideration the timing cycles of a pacemaker. The design analysis shows that the proposed model of pacemaker is highly efficient and consumes significantly less energy.

Rate-Responsive Cardiac Pacing: Technological Solutions and Their Applications

Modern cardiac pacemakers are equipped with a function that allows the heart rate to adapt to the current needs of the patient in situations of increased demand related to exercise and stress ("rate-response" function). This function may be based on a variety of mechanisms, such as a built-in accelerometer responding to increased chest movement or algorithms sensing metabolic demand for oxygen, analysis of intrathoracic impedance, and analysis of the heart rhythm (Q-T interval). The latest technologies in the field of rate-response functionality relate to the use of an accelerometer in leadless endocavitary pacemakers; in these devices, the accelerometer enables mapping of the mechanical wave of the heart's work cycle, enabling the pacemaker to correctly sense native impulses and stimulate the ventricles in synchrony with the cycles of atria and heart valves. Another modern system for synchronizing pacing rate with the patient's real-time needs requires a closed-loop system that continuously monitors changes in the dynamics of heart contractions. This article discusses the technical details of various solutions for detecting and responding to situations related to increased oxygen demand (e.g., exercise or stress) in implantable pacemakers, and reviews the results of clinical trials regarding the use of these algorithms.

An FPGA-based design for power efficient low delay rate adaptive pacemaker using accelerometer and heart rate sensor

This paper presents a power efficient, low delay and rate adaptive dual chamber pacemaker (PLRDPM) using heart rate and accelerometer sensor. In recent years, number of modifications have been done in the pacemaker design. However, design of an implantable device on an open source is still challenging. Through this paper, we are proposing a "proof of concept" for the design of PLRDPM on FPGA for improving the vital parameters: delay and power consumption. The proposed PLRDPM comprises of accelerometer and heart rate sensors to measure physical activity's effect on heart rate of the bradycardia patients. A rate adaptive pacing algorithm has been designed using two sensor's data, to reduce the delay and power consumption. However, delay in the responses of various components in the circuitry produces an accumulative delay effect in any practical circuit. The delay and the power consumption for the proposed PLRDPM are found to be 2.82 ns and 9 mW, respectively.