Experimental study of plane electrode thickness scaling for 3D vertical resistive random access memory

Reliability effects of lateral filament confinement by nano-scaling the oxide in memristive devices

Write-variability and resistance instability are major reliability concerns impeding implementation of oxide-based memristive devices in neuromorphic systems. The root cause of the reliability issues is the stochastic nature of conductive filament formation and dissolution, whose impact is particularly critical in the high resistive state (HRS). Optimizing the filament stability requires mitigating diffusive processes within the oxide, but these are unaffected by conventional electrode scaling. Here we propose a device design that laterally confines the switching oxide volume and thus the filament to 10 nm, which yields reliability improvements in our measurements and simulations. We demonstrate a 50% decrease in HRS write-variability for an oxide nano-fin device in our full factorial analysis of modulated current-voltage sweeps. Furthermore, we use ionic noise measurements to quantify the HRS filament stability against diffusive processes. The laterally confined filaments exhibit a change in the signal-to-noise ratio distribution with a shift to higher values. Our complementing kinetic Monte Carlo simulation of oxygen vacancy (re-)distribution for confined filaments shows improved noise behavior and elucidates the underlying physical mechanisms. While lateral oxide volume scaling down to filament sizes is challenging, our efforts motivate further examination and awareness of filament confinement effects in regards to reliability.

GeSe ovonic threshold switch: the impact of functional layer thickness and device size

Three-dimensional phase change memory (3D PCM), possessing fast-speed, high-density and nonvolatility, has been successfully commercialized as storage class memory. A complete PCM device is composed of a memory cell and an associated ovonic threshold switch (OTS) device, which effectively resolves the leakage current issue in the crossbar array. The OTS materials are chalcogenide glasses consisting of chalcogens such as Te, Se and S as central elements, represented by GeTe6, GeSe and GeS. Among them, GeSe-based OTS materials are widely utilized in commercial 3D PCM, their scalability, however, has not been thoroughly investigated. Here, we explore the miniaturization of GeSe OTS selector, including functional layer thickness scalability and device size scalability. The threshold switching voltage of the GeSe OTS device almost lineally decreases with the thinning of the thickness, whereas it hardly changes with the device size. This indicates that the threshold switching behavior is triggered by the electric field, and the threshold switching field of the GeSe OTS selector is approximately 105 V/μm, regardless of the change in film thickness or device size. Systematically analyzing the threshold switching field of Ge-S and Ge-Te OTSs, we find that the threshold switching field of the OTS device is larger than 75 V/μm, significantly higher than PCM devices (8.1-56 V/μm), such as traditional Ge2Sb2Te5, Ag-In-Sb-Te, etc. Moreover, the required electric field is highly correlated with the optical bandgap. Our findings not only serve to optimize GeSe-based OTS device, but also may pave the approach for exploring OTS materials in chalcogenide alloys.

Graphene-Edge Electrode on a Cu-Based Chalcogenide Selector for 3D Vertical Memristor Cells

Resistive memristors are considered to be key components in the hardware implementation of complex neuromorphic networks because of their simplicity, compactness, and manageable power dissipation. However, breakthroughs with respect to both the selector material technology and the bit-cost-effective three-dimensional (3D) device architecture are necessary to provide sufficient device density while maintaining the advantages of a two-terminal device. Despite substantial progress in the scaling of the memristor devices, the scaling potential of the selector materials remains unclear. A majority of the selector materials are unlikely to form conductive filaments, and the effect of the highly concentrated electrical fields on such materials is not well understood. In this study, the atomically thin graphene edge in a 3D vertical memory architecture is utilized to study the effect of highly focused electrical fields on a CuGeS chalcogenide selector layer. We demonstrate that additional interface resistance can improve the nonlinearity and reduce leakage current by almost three orders of magnitude; however, even a relatively low Cu⁺ ion density can adversely affect leakage because of the highly asymmetric electrode configuration. This study presents a meaningful step toward understanding the characteristics of mobile ions in solid chalcogenide electrolytes and the potential for ultrascaled selector devices.

Scalable cross-point resistive switching memory and mechanism through an understanding of H2O2/glucose sensing using an IrOx/Al2O3/W structure

The resistive switching characteristics of a scalable IrO_x/Al₂O₃/W cross-point structure and its mechanism for pH/H₂O₂ sensing along with glucose detection have been investigated for the first time. Porous IrO_x and Ir³⁺/Ir⁴⁺ oxidation states are observed via high-resolution transmission electron microscope, field-emission scanning electron spectroscopy, and X-ray photo-electron spectroscopy. The 20 nm-thick IrO_x devices in sidewall contact show consecutive long dc cycles at a low current compliance (CC) of 10 μA, multi-level operation with CC varying from 10 μA to 100 μA, and long program/erase endurance of >10⁹ cycles with 100 ns pulse width. IrO_x with a thickness of 2 nm in the IrO_x/Al₂O₃/SiO₂/p-Si structure has shown super-Nernstian pH sensitivity of 115 mV per pH, and detection of H₂O₂ over the range of 1-100 nM is also achieved owing to the porous and reduction-oxidation (redox) characteristics of the IrO_x membrane, whereas a pure Al₂O₃/SiO₂ membrane does not show H₂O₂ sensing. A simulation based on Schottky, hopping, and Fowler-Nordheim tunneling conduction, and a redox reaction, is proposed. The experimental I-V curve matches very well with simulation. The resistive switching mechanism is owing to O^2- ion migration, and the redox reaction of Ir³⁺/Ir⁴⁺ at the IrO_x/Al₂O₃ interface through H₂O₂ sensing as well as Schottky barrier height modulation is responsible. Glucose at a low concentration of 10 pM is detected using a completely new process in the IrO_x/Al₂O₃/W cross-point structure. Therefore, this cross-point memory shows a method for low cost, scalable, memory with low current, multi-level operation, which will be useful for future highly dense three-dimensional (3D) memory and as a bio-sensor for the future diagnosis of human diseases.

Graphene/h-BN Heterostructures for Vertical Architecture of RRAM Design

The development of RRAM is one of the mainstreams for next generation non-volatile memories to replace the conventional charge-based flash memory. More importantly, the simpler structure of RRAM makes it feasible to be integrated into a passive crossbar array for high-density memory applications. By stacking up the crossbar arrays, the ultra-high density of 3D horizontal RRAM (3D-HRAM) can be realized. However, 3D-HRAM requires critical lithography and other process for every stacked layer, and this fabrication cost overhead increases linearly with the number of stacks. Here, it is demonstrated that the 2D material-based vertical RRAM structure composed of graphene plane electrode/multilayer h-BN insulating dielectric stacked layers, AlOx/TiOx resistive switching layer and ITO pillar electrode exhibits reliable device performance including forming-free, low power consumption (Pset = ~2 μW and Preset = ~0.2 μW), and large memory window (>300). The scanning transmission electron microscopy indicates that the thickness of multilayer h-BN is around 2 nm. Due to the ultrathin-insulating dielectric and naturally high thermal conductivity characteristics of h-BN, the vertical structure combining the graphene plane electrode with multilayer h-BN insulating dielectric can pave the way toward a new area of ultra high-density memory integration in the future.

Metal oxide-resistive memory using graphene-edge electrodes

The emerging paradigm of ‘abundant-data' computing requires real-time analytics on enormous quantities of data collected by a mushrooming network of sensors. Todays computing technology, however, cannot scale to satisfy such big data applications with the required throughput and energy efficiency. The next technology frontier will be monolithically integrated chips with three-dimensionally interleaved memory and logic for unprecedented data bandwidth with reduced energy consumption. In this work, we exploit the atomically thin nature of the graphene edge to assemble a resistive memory (∼3 Å thick) stacked in a vertical three-dimensional structure. We report some of the lowest power and energy consumption among the emerging non-volatile memories due to an extremely thin electrode with unique properties, low programming voltages, and low current. Circuit analysis of the three-dimensional architecture using experimentally measured device properties show higher storage potential for graphene devices compared that of metal based devices.

Increasing memory performance and density will require new breakthroughs in atomic-scale technology and three-dimensional device architectures. Here, the authors demonstrate a memory just 3 Å thick that can be stacked by exploiting the atomically thin edge of monolayer graphene.

Stacked 3D RRAM Array with Graphene/CNT as Edge Electrodes

There are two critical challenges which determine the array density of 3D RRAM: 1) the scaling limit in both horizontal and vertical directions; 2) the integration of selector devices in 3D structure. In this work, we present a novel 3D RRAM structure using low-dimensional materials, including 2D graphene and 1D carbon nanotube (CNT), as the edge electrodes. A two-layer 3D RRAM with monolayer graphene as edge electrode is demonstrated. The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale. Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized. Furthermore, the discussion of high array density potential is presented.

Thermal crosstalk in 3-dimensional RRAM crossbar array

High density 3-dimensional (3D) crossbar resistive random access memory (RRAM) is one of the major focus of the new age technologies. To compete with the ultra-high density NAND and NOR memories, understanding of reliability mechanisms and scaling potential of 3D RRAM crossbar array is needed. Thermal crosstalk is one of the most critical effects that should be considered in 3D crossbar array application. The Joule heat generated inside the RRAM device will determine the switching behavior itself, and for dense memory arrays, the temperature surrounding may lead to a consequent resistance degradation of neighboring devices. In this work, thermal crosstalk effect and scaling potential under thermal effect in 3D RRAM crossbar array are systematically investigated. It is revealed that the reset process is dominated by transient thermal effect in 3D RRAM array. More importantly, thermal crosstalk phenomena could deteriorate device retention performance and even lead to data storage state failure from LRS (low resistance state) to HRS (high resistance state) of the disturbed RRAM cell. In addition, the resistance state degradation will be more serious with continuously scaling down the feature size. Possible methods for alleviating thermal crosstalk effect while further advancing the scaling potential are also provided and verified by numerical simulation.