Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth

A new and versatile template towards vertically oriented nanopillars and nanotubes

Vertically oriented nanostructures bring unparalleled high surface area, light trapping capability, and high device density to electronic, optoelectronic, and energy storage devices. However, general methods to prepare such structures remain sparse and are typically based on anodized metal oxide templates. Here, we demonstrate a new approach: using vertically oriented tetraaniline nanopillar arrays as templates for creating nanopillars and nanotubes of other materials. The tetraaniline templates are scalable and easy to prepare. Vertical arrays of a variety of materials can be created by directly coating them onto the tetraaniline nanopillars via vapor, solution, or electrodeposition. Since the tetraaniline template is encased within the target material, it does not require post-deposition removal, thus enabling vertical structure formation of sensitive materials. Conversely, removal of the encased tetraaniline template provides vertically oriented nanotube arrays in a lost-wax-type operation. The resulting vertical structures exhibit a high degree of orientation and height uniformity, with tunable feature size, spacing, and array density. Furthermore, the deposition location and shape of the vertical arrays can be patterned at a resolution of 3 μm. Collectively, these attributes should broaden the material repertoire for vertically oriented structures, and lead to advancements in energy storage, electronics, and optoelectronics.

Surface Nano-Patterning for the Bottom-Up Growth of III-V Semiconductor Nanowire Ordered Arrays

Ordered arrays of vertically aligned semiconductor nanowires are regarded as promising candidates for the realization of all-dielectric metamaterials, artificial electromagnetic materials, whose properties can be engineered to enable new functions and enhanced device performances with respect to naturally existing materials. In this review we account for the recent progresses in substrate nanopatterning methods, strategies and approaches that overall constitute the preliminary step towards the bottom-up growth of arrays of vertically aligned semiconductor nanowires with a controlled location, size and morphology of each nanowire. While we focus specifically on III-V semiconductor nanowires, several concepts, mechanisms and conclusions reported in the manuscript can be invoked and are valid also for different nanowire materials.

Poly(styrene)-block-Maltoheptaose Films for Sub-10 nm Pattern Transfer: Implications for Transistor Fabrication

Sequential infiltration synthesis (SIS) into poly(styrene)-block-maltoheptaose (PS-b-MH) block copolymer using vapors of trimethyl aluminum and water was used to prepare nanostructured surface layers. Prior to the infiltration, the PS-b-MH had been self-assembled into 12 nm pattern periodicity. Scanning electron microscopy indicated that horizontal alumina-like cylinders of 4.9 nm diameter were formed after eight infiltration cycles, while vertical cylinders were 1.3 nm larger. Using homopolymer hydroxyl-terminated poly(styrene) (PS-OH) and MH films, specular neutron reflectometry revealed a preferential reaction of precursors in the MH compared to PS-OH. The infiltration depth into the maltoheptaose homopolymer film was found to be 2.0 nm after the first couple of cycles. It reached 2.5 nm after eight infiltration cycles, and the alumina incorporation within this infiltrated layer corresponded to 23 vol % Al2O3. The alumina-like material, resulting from PS-b-MH infiltration, was used as an etch mask to transfer the sub-10 nm pattern into the underlying silicon substrate, to an aspect ratio of approximately 2:1. These results demonstrate the potential of exploiting SIS into carbohydrate-based polymers for nanofabrication and high pattern density applications, such as transistor devices.

Green Nanofabrication Opportunities in the Semiconductor Industry: A Life Cycle Perspective

The turn of the 21st century heralded in the semiconductor age alongside the Anthropocene epoch, characterised by the ever-increasing human impact on the environment. The ecological consequences of semiconductor chip manufacturing are the most predominant within the electronics industry. This is due to current reliance upon large amounts of solvents, acids and gases that have numerous toxicological impacts. Management and assessment of hazardous chemicals is complicated by trade secrets and continual rapid change in the electronic manufacturing process. Of the many subprocesses involved in chip manufacturing, lithographic processes are of particular concern. Current developments in bottom-up lithography, such as directed self-assembly (DSA) of block copolymers (BCPs), are being considered as a next-generation technology for semiconductor chip production. These nanofabrication techniques present a novel opportunity for improving the sustainability of lithography by reducing the number of processing steps, energy and chemical waste products involved. At present, to the extent of our knowledge, there is no published life cycle assessment (LCA) evaluating the environmental impact of new bottom-up lithography versus conventional lithographic techniques. Quantification of this impact is central to verifying whether these new nanofabrication routes can replace conventional deposition techniques in industry as a more environmentally friendly option.