Brain-Machine Interfaces: From Basic Science to Neuroprostheses and Neurorehabilitation

Brain-machine interfaces (BMIs) combine methods, approaches, and concepts derived from neurophysiology, computer science, and engineering in an effort to establish real-time bidirectional links between living brains and artificial actuators. Although theoretical propositions and some proof of concept experiments on directly linking the brains with machines date back to the early 1960s, BMI research only took off in earnest at the end of the 1990s, when this approach became intimately linked to new neurophysiological methods for sampling large-scale brain activity. The classic goals of BMIs are 1) to unveil and utilize principles of operation and plastic properties of the distributed and dynamic circuits of the brain and 2) to create new therapies to restore mobility and sensations to severely disabled patients. Over the past decade, a wide range of BMI applications have emerged, which considerably expanded these original goals. BMI studies have shown neural control over the movements of robotic and virtual actuators that enact both upper and lower limb functions. Furthermore, BMIs have also incorporated ways to deliver sensory feedback, generated from external actuators, back to the brain. BMI research has been at the forefront of many neurophysiological discoveries, including the demonstration that, through continuous use, artificial tools can be assimilated by the primate brain's body schema. Work on BMIs has also led to the introduction of novel neurorehabilitation strategies. As a result of these efforts, long-term continuous BMI use has been recently implicated with the induction of partial neurological recovery in spinal cord injury patients.

High speed digital interfacing for a neural data acquisition system

Diseases like schizophrenia and genetic epilepsy are supposed to be caused by disorders in the early development of the brain. For the further investigation of these relationships a custom designed application specific integrated circuit (ASIC) was developed that is optimized for the recording from neonatal mice [Bahr A, Abu-Saleh L, Schroeder D, Krautschneider W. 16 Channel Neural Recording Integrated Circuit with SPI Interface and Error Correction Coding. Proc. 9th BIOSTEC 2016. Biodevices: Rome, Italy, 2016; 1: 263; Bahr A, Abu-Saleh L, Schroeder D, Krautschneider W. Development of a neural recording mixed signal integrated circuit for biomedical signal acquisition. Biomed Eng Biomed Tech Abstracts 2015; 60(S1): 298–299; Bahr A, Abu-Saleh L, Schroeder D, Krautschneider WH. 16 Channel Neural Recording Mixed Signal ASIC. CDNLive EMEA 2015 Conference Proceedings, 2015.]. To enable the live display of the neural signals a multichannel neural data acquisition system with live display functionality is presented. It implements a high speed data transmission from the ASIC to a computer with a live display functionality. The system has been successfully implemented and was used in a neural recording of a head-fixed mouse.

Embedded neural recording with TinyOS-based wireless-enabled processor modules

To create a wireless neural recording system that can benefit from the continuous advancements being made in embedded microcontroller and communications technologies, an embedded-system-based architecture for wireless neural recording has been designed, fabricated, and tested. The system consists of commercial-off-the-shelf wireless-enabled processor modules (motes) for communicating the neural signals, and a back-end database server and client application for archiving and browsing the neural signals. A neural-signal-acquisition application has been developed to enable the mote to either acquire neural signals at a rate of 4000 12-bit samples per second, or detect and transmit spike heights and widths sampled at a rate of 16670 12-bit samples per second on a single channel. The motes acquire neural signals via a custom low-noise neural-signal amplifier with adjustable gain and high-pass corner frequency that has been designed, and fabricated in a 1.5-microm CMOS process. In addition to browsing acquired neural data, the client application enables the user to remotely toggle modes of operation (real-time or spike-only), as well as amplifier gain and high-pass corner frequency.

A low-power, low-noise neural-signal amplifier circuit in 90-nm CMOS

A fully-differential low-power low-noise preamplifier for biopotential and neural-recording applications is presented. This design, which has been simulated in a standard 90-nm CMOS process, consumes 30 microW from a 3-V power supply. The simulated integrated input-referred noise is 2.3 microV over 0.1 Hz to 20 kHz. The amplifier also provides an output swing of +/- 0.9 V with a THD of less than 0.1%