A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs

This study proposed a novel source/drain (S/D) extension scheme to increase the stress in nanosheet (NS) field-effect transistors (NSFETs) and investigated the scheme by using technology-computer-aided-design simulations. In three-dimensional integrated circuits, transistors in the bottom tier were exposed to subsequent processes; therefore, selective annealing, such as laser-spike annealing (LSA), should be applied. However, the application of the LSA process to NSFETs significantly decreased the on-state current (I_on) owing to diffusionless S/D dopants. Furthermore, the barrier height below the inner spacer was not lowered even under on-state bias conditions because ultra-shallow junctions between the NS and S/D were formed far from the gate metal. However, the proposed S/D extension scheme overcame these I_on reduction issues by adding an NS-channel-etching process before S/D formation. A larger S/D volume induced a larger stress in the NS channels; thus, the stress was boosted by over 25%. Additionally, an increase in carrier concentrations in the NS channels improved I_on. Therefore, I_on increased by approximately 21.7% (37.4%) in NFETs (PFETs) compared with NSFETs without the proposed scheme. Additionally, the RC delay was improved by 2.03% (9.27%) in NFETs (PFETs) compared with NSFETs using rapid thermal annealing. Therefore, the S/D extension scheme overcame the I_on reduction issues encountered in LSA and significantly enhanced the AC/DC performance.

A Survey of Near-Data Processing Architectures for Neural Networks

Data-intensive workloads and applications, such as machine learning (ML), are fundamentally limited by traditional computing systems based on the von-Neumann architecture. As data movement operations and energy consumption become key bottlenecks in the design of computing systems, the interest in unconventional approaches such as Near-Data Processing (NDP), machine learning, and especially neural network (NN)-based accelerators has grown significantly. Emerging memory technologies, such as ReRAM and 3D-stacked, are promising for efficiently architecting NDP-based accelerators for NN due to their capabilities to work as both high-density/low-energy storage and in/near-memory computation/search engine. In this paper, we present a survey of techniques for designing NDP architectures for NN. By classifying the techniques based on the memory technology employed, we underscore their similarities and differences. Finally, we discuss open challenges and future perspectives that need to be explored in order to improve and extend the adoption of NDP architectures for future computing platforms. This paper will be valuable for computer architects, chip designers, and researchers in the area of machine learning.

Highly Configurable 100 Channel Recording and Stimulating Integrated Circuit for Biomedical Experiments

This paper presents the design results of a 100-channel integrated circuit dedicated to various biomedical experiments requiring both electrical stimulation and recording ability. The main design motivation was to develop an architecture that would comprise not only the recording and stimulation, but would also block allowing to meet different experimental requirements. Therefore, both the controllability and programmability were prime concerns, as well as the main chip parameters uniformity. The recording stage allows one to set their parameters independently from channel to channel, i.e., the frequency bandwidth can be controlled in the (0.3 Hz-1 kHz)-(20 Hz-3 kHz) (slow signal path) or (0.3 Hz-1 kHz)-4.7 kHz (fast signal path) range, while the voltage gain can be set individually either to 43.5 dB or 52 dB. Importantly, thanks to in-pixel circuitry, main system parameters may be controlled individually allowing to mitigate the circuitry components spread, i.e., lower corner frequency can be tuned in the 54 dB range with approximately 5% precision, and the upper corner frequency spread is only 4.2%, while the voltage gain spread is only 0.62%. The current stimulator may also be controlled in the broad range (69 dB) with its current setting precision being no worse than 2.6%. The recording channels' input-referred noise is equal to 8.5 µVRMS in the 10 Hz-4.7 kHz bandwidth. The single-pixel occupies 0.16 mm2 and consumes 12 µW (recording part) and 22 µW (stimulation blocks).

A moisture-enabled fully printable power source inspired by electric eels

Great efforts have been made to build integrated devices to enable future wearable electronics; however, safe, disposable, and cost-effective power sources still remain a challenge. In this paper, an all-solid-state power source was developed by using graphene materials and can be printed directly on an insulating substrate such as paper. The design of the power source was inspired by electric eels to produce programmable voltage and current by converting the chemical potential energy of the ion gradient to electric energy in the presence of moisture. An ultrahigh voltage of 192 V with 175 cells in series printed on a strip of paper was realized under ambient conditions. For the planar cell, the mathematical fractal design concept was adapted as printed patterns, improving the output power density to 2.5 mW cm^-3, comparable to that of lithium thin-film batteries. A foldable three-dimensional (3D) cell was also achieved by employing an origami strategy, demonstrating a versatile design to provide green electric energy. Unlike typical batteries, this power source printed on flexible paper substrate does not require liquid electrolytes, hazardous components, or complicated fabrication processes and is highly customizable to meet the demands of wearable electronics and Internet of Things applications.

Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (L_ch), thickness of silicon body (T_si), and doping concentration (N_ch) of the channel region below the gate are adjusted. As a result, the memory window increases as L_ch and T_si increase, and the memory window is minimum when N_ch is approximately 9 × 10¹⁹ cm⁻³. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (T_ILD), T_si, L_ch, and N_ch. The variation of propagation delay of the M3DINV with different T_ILD, T_si, L_ch, and N_ch is also investigated. As a result, the electrical coupling between the stacked FBFETs by T_ILD can be neglected. The switching voltage gaps increase as L_ch and T_si increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as T_si and N_ch increase. For transient response, t_pHL decrease as L_ch, T_si, and N_ch increase, but t_pLH increase as L_ch and T_si increase and it is almost the same for N_ch.

3D Defect Localization on Exothermic Faults within Multi-Layered Structures Using Lock-In Thermography: An Experimental and Numerical Approach

Micro-electronic devices are increasingly incorporating miniature multi-layered integrated architectures. However, the localization of faults in three-dimensional structure remains challenging. This study involved the experimental and numerical estimation of the depth of a thermally active heating source buried in multi-layered silicon wafer architecture by using both phase information from an infrared microscopy and finite element simulation. Infrared images were acquired and real-time processed by a lock-in method. It is well known that the lock-in method can increasingly improve detection performance by enhancing the spatial and thermal resolution of measurements. Operational principle of the lock-in method is discussed, and it is represented that phase shift of the thermal emission from a silicon wafer stacked heat source chip (SSHSC) specimen can provide good metrics for the depth of the heat source buried in SSHSCs. Depth was also estimated by analyzing the transient thermal responses using the coupled electro-thermal simulations. Furthermore, the effects of the volumetric heat source configuration mimicking the 3D through silicon via integration package were investigated. Both the infrared microscopic imaging with the lock-in method and FE simulation were potentially useful for 3D isolation of exothermic faults and their depth estimation for multi-layered structures, especially in packaged semiconductors.

Design and fabrication of vertically-integrated CMOS image sensors

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

Optical interconnects to electronic chips

Optical interconnects are progressively replacing wires at shorter and shorter distances in information processing machines. This paper summarizes the progress toward and prospects for the penetration of optics all the way to the silicon chip.

Parametric yield management for 3D ICs

Three-Dimensional (3D) Integrated Circuits (ICs) that integrate die with Through-Silicon Vias (TSVs) promise to continue system and functionality scaling beyond the traditional geometric 2D device scaling. 3D integration also improves the performance of ICs by reducing the communication time between different chip components through the use of short TSV-based vertical wires. This reduction is particularly attractive in processors where it is desirable to reduce the access time between the main logic die and the L2 cache or the main memory die. Process variations in 2D ICs lead to a drop in parametric yield (as measured by speed, leakage and sales profits), which forces manufacturers to speed bin their chips and to sell slow chips at reduced prices. In this paper we develop a model to quantify the impact of process variations on the parametric yield of 3D ICs, and then we propose a number of integration strategies that use a graph-theoretic framework to maximize the performance, parametric yield and profits of 3D ICs. Comparing our proposed strategies to current yield-oblivious methods, it is demonstrated that it is possible to increase the number of 3D ICs in the fastest speed bins by almost 2×, while simultaneously reducing the number of slow ICs by 29.4%. This leads to an improvement in performance by up to 6.45% and an increase of about 12.48% in total sales revenue using up-to-date market price models.

Layer-by-layer assembly of nanowires for three-dimensional, multifunctional electronics

We report a general approach for three-dimensional (3D) multifunctional electronics based on the layer-by-layer assembly of nanowire (NW) building blocks. Using germanium/silicon (Ge/Si) core/shell NWs as a representative example, ten vertically stacked layers of multi-NW field-effect transistors (FETs) were fabricated. Transport measurements demonstrate that the Ge/Si NW FETs have reproducible high-performance device characteristics within a given device layer, that the FET characteristics are not affected by sequential stacking, and importantly, that uniform performance is achieved in sequential layers 1 through 10 of the 3D structure. Five-layer single-NW FET structures were also prepared by printing Ge/Si NWs from lower density growth substrates, and transport measurements showed similar high-performance characteristics for the FETs in layers 1 and 5. In addition, 3D multifunctional circuitry was demonstrated on plastic substrates with sequential layers of inverter logical gates and floating gate memory elements. Notably, electrical characterization studies show stable writing and erasing of the NW floating gate memory elements and demonstrate signal inversion with larger than unity gain for frequencies up to at least 50 MHz. The ability to assemble reproducibly sequential layers of distinct types of NW-based devices coupled with the breadth of NW building blocks should enable the assembly of increasing complex multilayer and multifunctional 3D electronics in the future.