Design of a Second Generation Firewire Based Data Acquisition System for Small Animal PET Scanners

FPGA-Based Pulse Pile-Up Correction With Energy and Timing Recovery

Modern field programmable gate arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates well above 100 MHz. This, combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilized to add significant signal processing power to produce higher quality images. In this paper we report on an all-digital pulse pile-up correction algorithm that has been developed for the FPGA. The pile-up mitigation algorithm will allow the scanner to run at higher count rates without incurring large data losses due to the overlapping of scintillation signals. This correction technique utilizes a reference pulse to extract timing and energy information for most pile-up events. Using pulses acquired from a Zecotech Photonics MAPD-N with an LFS-3 scintillator, we show that good timing and energy information can be achieved in the presence of pile-up utilizing a moderate amount of FPGA resources.

A CMOS ASIC Design for SiPM Arrays

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

Evolution of the Design of a Second Generation FireWire Based Data Acquisition System

Our laboratory has previously reported on the basic design concepts of an updated FireWire based data acquisition system for depth-of-interaction detector systems designed at the University of Washington. The new version of our data acquisition system leverages the capabilities of modern field programmable gate arrays (FPGA) and puts almost all functions into the FPGA, including the FireWire elements, the embedded processor, and pulse timing and integration. The design is centered around an acquisition node board (ANB) that includes 64 serial ADC channels, one high speed parallel ADC, FireWire 1394b support, the FPGA, a serial command bus and signal lines to support a rough coincidence window implementation to reject singles events from being sent on the FireWire bus. Adapter boards convert detector signals into differential paired signals to connect to the ANB. In this paper we discuss many of the design details, including steps taken to minimize the number of layers in the printed circuit board and to avoid skewing of parallel signals and unwanted bandwidth limitations.

FPGA-Based Pulse Pileup Correction

Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this next generation scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper we report on an all-digital pulse pileup correction algorithm that is being developed for the FPGA. The pileup mitigation algorithm will allow the scanner to run at higher count rates without incurring large data losses due to the overlapping of scintillation signals. This correction technique utilizes a reference pulse to extract timing and energy information for most pileup events. Using pulses were acquired from a Zecotech Photonics MAPDN with an LFS-3 scintillator, we show that good timing and energy information can be achieved in the presence of pileup.

FPGA-Based Pulse Parameter Discovery for Positron Emission Tomography

Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex digital signal processing algorithms with clock rates well above 100MHz. This, combined with FPGA's low expense and ease of use make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a series of high-resolution, small-animal PET scanners that utilize FPGAs as the core of the front-end electronics. For these next generation scanners, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper we report how we utilize the reconfigurable property of an FPGA to self-calibrate itself to determine pulse parameters necessary for some of the pulse processing steps. Specifically, we show how the FPGA can generate a reference pulse based on actual pulse data instead of a model. We also report how other properties of the photodetector pulse (baseline, pulse length, average pulse energy and event triggers) can be determined automatically by the FPGA.

An 8×8 Row-Column Summing Readout Electronics for Preclinical Positron Emission Tomography Scanners

This work presents a row/column summing readout electronics for an 8×8 silicon photomultiplier array. The summation circuit greatly reduces the number of electronic channels, which is desirable for pursuing higher resolution positron emission tomography scanners. By using a degenerated common source topology in the summation circuit, more fan-in is possible and therefore a greater reduction in the number of electronic channels can be achieved. The timing signal is retrieved from a common anode, which allows the use of a single fast-sampling analog to digital converter (ADC) for the timing channel and slower, lower power ADCs for the 64 spatial channels. Preliminary results of one row summation of the 8×8 readout electronics exhibited FWHM energy resolution of 17.8% and 18.3% with and without multiplexing, respectively. The measured timing resolution is 2.9ns FWHM.