Integrated high-voltage inductive power and data-recovery front end dedicated to implantable devices

Low-Radiation Cellular Inductive Powering of Rodent Wireless Brain Interfaces: Methodology and Design Guide

This paper presents a general methodology of inductive power delivery in wireless chronic rodent electrophysiology applications. The focus is on such systems design considerations under the following key constraints: maximum power delivery under the allowable specific absorption rate (SAR), low cost and spatial scalability. The methodology includes inductive coil design considerations within a low-frequency ferrite-core-free power transfer link which includes a scalable coil-array power transmitter floor and a single-coil implanted or worn power receiver. A specific design example is presented that includes the concept of low-SAR cellular single-transmitter-coil powering through dynamic tracking of a magnet-less receiver spatial location. The transmitter coil instantaneous supply current is monitored using a small number of low-cost electronic components. A drop in its value indicates the proximity of the receiver due to the reflected impedance of the latter. Only the transmitter coil nearest to the receiver is activated. Operating at the low frequency of 1.5 MHz, the inductive powering floor delivers a maximum of 15.9 W below the IEEE C95 SAR limit, which is over three times greater than that in other recently reported designs. The power transfer efficiency of 39% and 13% at the nominal and maximum distances of 8 cm and 11 cm, respectively, is maintained.

An Integrated Wireless Power Management and Data Telemetry IC for High-Compliance-Voltage Electrical Stimulation Applications

This paper describes a 13.56-MHz wireless power recovery system with bidirectional data link for high-compliance-voltage neural/muscle stimulator. The power recovery circuit includes a 2-stage rectifier, 2 LDOs and a high voltage charge pump to provide 3 DC outputs: 1.8 V, 3.3 V and 20 V for the stimulator. A 2-stage time division based rectifier is proposed to provide 3 DC outputs simultaneously. It improves the power efficiency without introducing any impact on the forward data recovery. The 20 V output is generated by a modified low ripple charge pump that reduces the ripple voltage by 40%. The power management system shows 49% peak power efficiency. The data link includes a clock and data recovery (CDR) circuit and a load shift keying (LSK) modulator for bidirectional data telemetry. The forward and backward data rates of the data telemetry are 61.5 kbps and 33.3 kbps, respectively. In addition, a power monitor circuit for closed-loop power control is implemented. The whole system has been fabricated in a 24 V HV LDMOS option 1.8 μ m CMOS process, occupying a core area of around 3.5 mm (2).

An On-Chip Multi-Voltage Power Converter With Leakage Current Prevention Using 0.18 μm High-Voltage CMOS Process

In this paper, we present an on-chip multi-voltage power converter incorporating of a quad-voltage timing-control rectifier and regulators to produce ±12 V and ±1.8 V simultaneously through inductive powering. The power converter achieves a PCE of 77.3% with the delivery of more than 100 mW to the implant. The proposed rectifier adopts a two-phase start-up scheme and mixed-voltage gate controller to avoid substrate leakage current. This current cannot be prevented by the conventional dynamic substrate biasing technique when using the high-voltage CMOS process with transistor threshold voltage higher than the turn-on voltage of parasitic diodes. High power conversion efficiency is achieved by 1) substrate leakage current prevention, 2) operating all rectifying transistors as switches with boosted gate control voltages, and 3) compensating the delayed turn-on and preventing reverse leakage current of rectifying switches with the proposed look-ahead comparator. This chip occupies an area of 970 μm × 4500 μm in a 0.18 μ m 32 V HV CMOS process. The quad-voltage timing-control rectifier alone is able to output a high DC voltage at the range of [2.5 V, 25 V]. With this power converter, both bench-top experiment and in-vivo power link test using a rat model were validated.

A 10.5 cm ultrasound link for deep implanted medical devices

A study on ultrasound link for wireless energy transmission dedicated to deeply implanted medical devices is presented. The selection of the frequency to avoid biological side effects (e.g., cavitations), the choice of the power amplifier to drive the external transducers and the design of the rectifier to maximize the energy extraction from the implanted transducer are described in details. The link efficiency is characterized in water using a phantom material for a transmitter-receiver distance of 105 mm, transducers active area of 30 mm × 96 mm and 5 mm × 10 mm, respectively, and a system efficiency of 1.6% is measured.

A 24 Vpp compliant biphasic stimulator for inductively powered animal behavior studies

Stimulation of biological neurons using electrical charges has gained popularity in neuro-engineering studies. Wireless power delivery to electrical stimulators is an essential requirement for long term and maintenance-free implantable applications. Voltage compliance is often a limiting factor in these systems. We present an inductively powered biphasic stimulator that is capable of exhibiting 24 Vpp load voltage compliance, while harvesting up to 13 V. The stimulator can deliver currents ranging from 10 µA to 6 mA. The inductive energy harvesting system operates at a low carrier frequency of 134.2 KHz for enhanced depth of penetration in biological medium. The near-field harvester works reliably for up to 50 mm inter-antenna distance. Noise performance and charge balancing accuracy have also been improved due to the absence of a boost switching circuit and floating current source based architecture. In-vivo motor and visual cortex stimulations have been performed using epi-dural screw electrodes on an awake behaving and anesthetized Wister rat.

A high frequency active voltage doubler in standard CMOS using offset-controlled comparators for inductive power transmission

In this paper, we present a fully integrated active voltage doubler in CMOS technology using offset-controlled high speed comparators for extending the range of inductive power transmission to implantable microelectronic devices (IMD) and radio-frequency identification (RFID) tags. This active voltage doubler provides considerably higher power conversion efficiency (PCE) and lower dropout voltage compared to its passive counterpart and requires lower input voltage than active rectifiers, leading to reliable and efficient operation with weakly coupled inductive links. The offset-controlled functions in the comparators compensate for turn-on and turn-off delays to not only maximize the forward charging current to the load but also minimize the back current, optimizing PCE in the high frequency (HF) band. We fabricated the active voltage doubler in a 0.5-μm 3M2P std . CMOS process, occupying 0.144 mm(2) of chip area. With 1.46 V peak AC input at 13.56 MHz, the active voltage doubler provides 2.4 V DC output across a 1 kΩ load, achieving the highest PCE = 79% ever reported at this frequency. In addition, the built-in start-up circuit ensures a reliable operation at lower voltages.

Toward a fully integrated neurostimulator with inductive power recovery front-end

In order to investigate new neurostimulation strategies for micturition recovery in spinal cord injured patients, custom implantable stimulators are required to carry-on chronic animal experiments. However, higher integration of the neurostimulator becomes increasingly necessary for miniaturization purposes, power consumption reduction, and for increasing the number of stimulation channels. As a first step towards total integration, we present in this paper the design of a highly-integrated neurostimulator that can be assembled on a 21-mm diameter printed circuit board. The prototype is based on three custom integrated circuits fabricated in High-Voltage (HV) CMOS technology, and a low-power small-scale commercially available FPGA. Using a step-down approach where the inductive voltage is left free up to 20 V, the inductive power and data recovery front-end is fully integrated. In particular, the front-end includes a bridge rectifier, a 20-V voltage limiter, an adjustable series regulator (5 to 12 V), a switched-capacitor step-down DC/DC converter (1:3, 1:2, or 2:3 ratio), as well as data recovery. Measurements show that the DC/DC converter achieves more than 86% power efficiency while providing around 3.9-V from a 12-V input at 1-mA load, 1:3 conversion ratio, and 50-kHz switching frequency. With such efficiency, the proposed step-down inductive power recovery topology is more advantageous than its conventional step-up counterpart. Experimental results confirm good overall functionality of the system.

An Adaptive Reconfigurable Active Voltage Doubler/Rectifier for Extended-Range Inductive Power Transmission

We present an adaptive reconfigurable active voltage doubler (VD)/rectifier (REC) (VD/REC) in standard CMOS, which can adaptively change its topology to either a VD or a REC by sensing the output voltage, leading to more robust inductive power transmission over an extended range. Both active VD and REC modes provide much lower dropout voltage and far better power conversion efficiency (PCE) compared to their passive counterparts by adopting offset-controlled high-speed comparators that drive the rectifying switches at proper times in the high-frequency band. We have fabricated the active VD/REC in a 0.5-µm 3-metal 2-poly CMOS process, occupying 0.585 mm² of chip area. In an exemplar setup, VD/REC extended the power transmission range by 33% (from 6 to 8 cm) in relative coil distance and 41.5% (from 53° to 75°) in relative coil orientation compared to using the REC alone. While providing 3.1-V dc output across a 500-Ω load from 2.15- (VD) and 3.7-V (REC) peak ac inputs at 13.56 MHz, VD/REC achieved measured PCEs of 70% and 77%, respectively.