A CMOS power-efficient low-noise current-mode front-end amplifier for neural signal recording

A current-mode system to self-measure temperature on implantable optoelectronics

BACKGROUND

One of the major concerns in implantable optoelectronics is the heat generated by emitters such as light emitting diodes (LEDs). Such devices typically produce more heat than light, whereas medical regulations state that the surface temperature change of medical implants must stay below + 2 °C. The LED's reverse current can be employed as a temperature-sensitive parameter to measure the temperature change at the implant's surface, and thus, monitor temperature rises. The main challenge in this approach is to bias the LED with a robust voltage since the reverse current is strongly and nonlinearly sensitive to the bias voltage.

METHODS

To overcome this challenge, we have developed an area-efficient LED-based temperature sensor using the LED as its own sensor and a CMOS electronic circuit interface to ensure stable bias and current measurement. The circuit utilizes a second-generation current conveyor (CCII) configuration to achieve this and has been implemented in 0.35 μm CMOS technology.

RESULTS

The developed circuits have been experimentally characterized, and the temperature-sensing functionality has been tested by interfacing different mini-LEDs in saline models of tissue prior to in vivo operation. The experimental results show the functionality of the CMOS electronics and the efficiency of the CCII-based technique with an operational frequency up to 130 kHz in achieving a resolution of 0.2 °C for the surface temperature up to + 45 °C.

CONCLUSIONS

We developed a robust CMOS current-mode sensor interface which has a reliable CCII to accurately convey the LED's reverse current. It is low power and robust against power supply ripple and transistor mismatch which makes it reliable for sensor interface. The achieved results from the circuit characterization and in vivo experiments show the feasibility of the whole sensor interface in monitoring the tissue surface temperature in optogenetics.

Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier

We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m² input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB.

A High Input Impedance Low Noise Integrated Front-End Amplifier for Neural Monitoring

Within neural monitoring systems, the front-end amplifier forms the critical element for signal detection and pre-processing, which determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a novel combined feedback loop-controlled approach is proposed to compensate for input leakage currents generated by low noise amplifiers when in integrated circuit form alongside signal leakage into the input bias network. This loop topology ensures the Front-End Amplifier (FEA) maintains a high input impedance across all manufacturing and operational variations. Measured results from a prototype manufactured on the AMS 0.35 [Formula: see text] CMOS technology is provided. This FEA consumes 3.1 [Formula: see text] in 0.042 [Formula: see text], achieves input impedance of 42 [Formula: see text], and 18.2 [Formula: see text] input-referred noise.

A Low Noise Amplifier for Neural Spike Recording Interfaces

This paper presents a Low Noise Amplifier (LNA) for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between power, area and noise. Additionally, this work introduces a novel transistor-level synthesis methodology for LNAs tailored for the minimization of their noise efficiency factor under area and noise constraints. The proposed LNA has been implemented in a 130 nm CMOS technology and occupies 0.053 mm-sq. Experimental results show that the LNA offers a noise efficiency factor of 2.16 and an input referred noise of 3.8 μVrms for 1.2 V power supply. It provides a gain of 46 dB over a nominal bandwidth of 192 Hz–7.4 kHz and consumes 1.92 μW. The performance of the proposed LNA has been validated through in vivo experiments with animal models.

A Low Power Linear Phase Programmable Long Delay Circuit

A novel linear phase programmable delay is being proposed and implemented in a 0.35 μm CMOS process. The delay line consists of N cascaded cells, each of which delays the input signal by Td/N, where Td is the total line delay. The delay generated by each cell is programmable by changing a clock frequency and is also fully independent of the frequency of the input signal. The total delay hence depends only on the chosen clock frequency and the total number of cascaded cells. The minimum clock frequency is limited by the maximum time a voltage signal can effectively be held by an individual cell. The maximum number of cascaded cells will be limited by the effects of accumulated offset due to transistor mismatch, which eventually will affect the operating mode of the individual transistors in a cell. This latter limitation has however been dealt with in the topology by having an offset compensation mechanism that makes possible having a large number of cascaded cells and hence a long resulting delay. The delay line has been designed for scalp-based neural activity analysis that is predominantly in the sub-100 Hz frequency range. For these signals, the delay generated by a 31-cell cascade has been demonstrated to be programmable from 30 ms to 3 s. Measurement results demonstrate a 31 stage, 50 Hz bandwidth, 0.3 s delay that operates from a 1.1 V supply with power consumption of 270 nW.

Advances in Microelectronics for Implantable Medical Devices

Implantable medical devices provide therapy to treat numerous health conditions as well as monitoring and diagnosis. Over the years, the development of these devices has seen remarkable progress thanks to tremendous advances in microelectronics, electrode technology, packaging and signal processing techniques. Many of today’s implantable devices use wireless technology to supply power and provide communication. There are many challenges when creating an implantable device. Issues such as reliable and fast bidirectional data communication, efficient power delivery to the implantable circuits, low noise and low power for the recording part of the system, and delivery of safe stimulation to avoid tissue and electrode damage are some of the challenges faced by the microelectronics circuit designer. This paper provides a review of advances in microelectronics over the last decade or so for implantable medical devices and systems. The focus is on neural recording and stimulation circuits suitable for fabrication in modern silicon process technologies and biotelemetry methods for power and data transfer, with particular emphasis on methods employing radio frequency inductive coupling. The paper concludes by highlighting some of the issues that will drive future research in the field.