A 2.4 GHz ULP reconfigurable asymmetric transceiver for single-chip wireless neural recording IC

System anti-jamming technology in the design of intelligent single chip computer constant current source of field strength machine

With the development of the electric power industry, the technical level of automatic testing equipment for the reliability of electrical component circuit breakers in the transmission and distribution network is getting higher and higher. The stability and accuracy of the test power supply are the basis for ensuring the pass rate of the test product. Most of the electrical testing and testing equipment has defects such as inaccurate power supply current regulation, low power, and low level of intelligence, which are difficult to meet the testing requirements. Based on the theory of a closed-loop control system, this paper adopts embedded system design technology to realize a high-current, high-power, high-stability digital constant current source system for line detection. This paper studies the rule-based intelligent anti-jamming decision engine design and system anti-jamming performance analysis of NC-OFDM system. We give the design of an intelligent anti-jamming decision engine based on rule-based decision-making, and focus on two intelligent anti-jamming decision-making algorithms: Adaptive Modulation and Coding (AMC) algorithm based on signal-to-noise ratio difference and packet error rate and Adaptive Sub-Band Selection (ASBS) algorithm. Experimental test results show that the output current range is 200 mA to 2000 mA, the system has realized a microstep adjustment of±5 mA, and the absolute error of current measurement is less than 0.3%+4 mA. The system is stable and reliable, and has high practical value in the field of high precision and low power.

A 400 MHz Wireless Neural Signal Processing IC With 625 $\times$ On-Chip Data Reduction and Reconfigurable BFSK/QPSK Transmitter Based on Sequential Injection Locking

An 8-channel wireless neural signal processing IC, which can perform real-time spike detection, alignment, and feature extraction, and wireless data transmission is proposed. A reconfigurable BFSK/QPSK transmitter (TX) at MICS/MedRadio band is incorporated to support different data rate requirement. By using an Exponential Component-Polynomial Component (EC-PC) spike processing unit with an incremental principal component analysis (IPCA) engine, the detection of neural spikes with poor SNR is possible while achieving 625× data reduction. For the TX, a dual-channel at 401 MHz and 403.8 MHz are supported by applying sequential injection locked techniques while attaining phase noise of -102 dBc/Hz at 100 kHz offset. From the measurement, error vector magnitude (EVM) of 4.60%/9.55% with power amplifier (PA) output power of -15 dBm is achieved for the QPSK at 8 Mbps and the BFSK at 12.5 kbps. Fabricated in 65 nm CMOS with an active area of 1 mm ², the design consumes a total current of 5  ∼ 5.6 mA with a maximum energy efficiency of 0.7 nJ/b.

A 11 mW 2.4 GHz 0.18 µm CMOS Transceivers for Wireless Sensor Networks

In this paper, a low power transceiver for wireless sensor networks (WSN) is proposed. The system is designed with fully functional blocks including a receiver, a fractional-N frequency synthesizer, and a class-E transmitter, and it is optimized with a good balance among output power, sensitivity, power consumption, and silicon area. A transmitter and receiver (TX-RX) shared input-output matching network is used so that only one off-chip inductor is needed in the system. The power and area efficiency-oriented, fully-integrated frequency synthesizer is able to provide programmable output frequencies in the 2.4 GHz range while occupying a small silicon area. Implemented in a standard 0.18 μm RF Complementary Metal Oxide Semiconductor (CMOS) technology, the whole transceiver occupies a chip area of 0.5 mm² (1.2 mm² including bonding pads for a QFN package). Measurement results suggest that the design is able to work at amplitude shift keying (ASK)/on-off-keying (OOK) and FSK modes with up to 500 kbps data rate. With an input sensitivity of −60 dBm and an output power of 3 dBm, the receiver, transmitter and frequency synthesizer consumes 2.3 mW, 4.8 mW, and 3.9 mW from a 1.8 V supply voltage, respectively.

A short-impulse UWB BPSK transmitter for large-scale neural recording implants

In this paper, a short-impulse ultra-wide band (UWB) transmitter is introduced to enable large-scale neural recordings within miniature brain implants including thousands of channels. The proposed impulse radio UWB transmitter uses a BPSK modulation scheme, the carrier signal of which uses only two delayed impulses to encode the transmitted signal. The proposed UWB transmitter has been implemented into a CMOS 180 nm technology. It occupies 300 μm × 230 μm, and consumes only 6.7 pJ/bit from a 1.8-V supply. Experimental results show that the transmitter has a bandwidth of 2.6 GHz to 5.6 GHz and achieves a maximum data rate of 800 Mbps, which outperforms existing low-power UWB transmitters for similar applications.

A 128-Channel Extreme Learning Machine-Based Neural Decoder for Brain Machine Interfaces

Currently, state-of-the-art motor intention decoding algorithms in brain-machine interfaces are mostly implemented on a PC and consume significant amount of power. A machine learning coprocessor in 0.35- μm CMOS for the motor intention decoding in the brain-machine interfaces is presented in this paper. Using Extreme Learning Machine algorithm and low-power analog processing, it achieves an energy efficiency of 3.45 pJ/MAC at a classification rate of 50 Hz. The learning in second stage and corresponding digitally stored coefficients are used to increase robustness of the core analog processor. The chip is verified with neural data recorded in monkey finger movements experiment, achieving a decoding accuracy of 99.3% for movement type. The same coprocessor is also used to decode time of movement from asynchronous neural spikes. With time-delayed feature dimension enhancement, the classification accuracy can be increased by 5% with limited number of input channels. Further, a sparsity promoting training scheme enables reduction of number of programmable weights by ≈ 2X.

A Single-Chip Full-Duplex High Speed Transceiver for Multi-Site Stimulating and Recording Neural Implants

We present a novel, fully-integrated, low-power full-duplex transceiver (FDT) to support high-density and bidirectional neural interfacing applications (high-channel count stimulating and recording) with asymmetric data rates: higher rates are required for recording (uplink signals) than stimulation (downlink signals). The transmitter (TX) and receiver (RX) share a single antenna to reduce implant size and complexity. The TX uses impulse radio ultra-wide band (IR-UWB) based on an edge combining approach, and the RX uses a novel 2.4-GHz on-off keying (OOK) receiver. Proper isolation (>20 dB) between the TX and RX path is implemented 1) by shaping the transmitted pulses to fall within the unregulated UWB spectrum (3.1-7 GHz), and 2) by space-efficient filtering (avoiding a circulator or diplexer) of the downlink OOK spectrum in the RX low-noise amplifier. The UWB 3.1-7 GHz transmitter can use either OOK or binary phase shift keying (BPSK) modulation schemes. The proposed FDT provides dual band 500-Mbps TX uplink data rate and 100 Mbps RX downlink data rate, and it is fully integrated into standard TSMC 0.18- μm CMOS within a total size of 0.8 mm(2). The total measured power consumption is 10.4 mW in full duplex mode (5 mW at 100 Mbps for RX, and 5.4 mW at 500 Mbps or 10.8 pJ/bit for TX). Additionally, a 3-coil inductive link along with on-chip power management circuits allows to powering up the implantable transceiver wirelessly by delivering 25 mW extracted from a 13.56-MHz carrier signal, at a total efficiency of 41.6%.

Design and Experimental Investigation of a Compact Circularly Polarized Integrated Filtering Antenna for Wearable Biotelemetric Devices

A compact circularly polarized (CP) integrated filtering antenna is reported for wearable biotelemetric devices in the 2.4 GHz ISM band. The design is based on a mutual synthesis of a CP patch antenna connected to a bandpass filter composed of coupled stripline open-loop resonators, which provides an integrated low-profile radiating and filtering module with a compact form factor of 0.44λ(0)×0.44λ(0)×0.04λ(0). The optimized filtering antenna is fabricated and measured, achieving an S11 < -14 dB, an axial ratio of less than 3 dB and gain higher than 3.5 dBi in the targeted ISM band. With the integrated filtering functionality, the antenna exhibits good out-of-band rejection over an ultra-wide frequency range of 1-6 GHz. Further full-wave simulations and experiments were carried out, verifying that the proposed filtering antenna maintains these desirable properties even when mounted in close proximity to the human body at different positions. The stable impedance performance and the simultaneous wide axial ratio and radiated power beam widths make it an ideal candidate as a wearable antenna for off-body communications. The additional integrated filtering functionality further improves utility by greatly reducing interference and crosstalk with other existing wireless systems.

A 16-Channel Nonparametric Spike Detection ASIC Based on EC-PC Decomposition

In extracellular neural recording experiments, detecting neural spikes is an important step for reliable information decoding. A successful implementation in integrated circuits can achieve substantial data volume reduction, potentially enabling a wireless operation and closed-loop system. In this paper, we report a 16-channel neural spike detection chip based on a customized spike detection method named as exponential component-polynomial component (EC-PC) algorithm. This algorithm features a reliable prediction of spikes by applying a probability threshold. The chip takes raw data as input and outputs three data streams simultaneously: field potentials, band-pass filtered neural data, and spiking probability maps. The algorithm parameters are on-chip configured automatically based on input data, which avoids manual parameter tuning. The chip has been tested with both in vivo experiments for functional verification and bench-top experiments for quantitative performance assessment. The system has a total power consumption of 1.36 mW and occupies an area of 6.71 mm (2) for 16 channels. When tested on synthesized datasets with spikes and noise segments extracted from in vivo preparations and scaled according to required precisions, the chip outperforms other detectors. A credit card sized prototype board is developed to provide power and data management through a USB port.

30 pJ/b, 67 Mbps, Centimeter-to-Meter Range Data Telemetry With an IR-UWB Wireless Link

This paper reports an energy-efficient, impulse radio ultra wideband (IR-UWB) wireless link operating in 3-5 GHz for data telemetry over centimeter-to-meter range distances at rates extended to tens of Mbps. The link comprises an all-digital, integrated transmitter (TX) fabricated in 90 nm 1P/9M CMOS that incorporates a waveform-synthesis pulse generator and a timing generator for on-off-keying (OOK) pulse modulation and phase scrambling. The link also incorporates an energy-detection receiver (RX) realized with commercial off-the-shelf (COTS) components that performs radio-frequency (RF) filtering, amplification, logarithmic power detection for data demodulation and automatic level control for robust operation in the presence of distance variations. Employing a miniaturized, UWB, chip antenna for the TX and RX, wireless transmission of pseudo-random binary sequence (PRBS) data at rates up to 50 Mbps over 10 cm-1 m is shown. Further, employing a high-gain horn antenna for the RX, wireless transmission of PRBS data at rates up to 67 Mbps over 50 cm-4 m is shown with a TX energy consumption of 30 pJ/b (i.e., power consumption of 2 mW) from 1.2 V. The measured bit error rate (BER) in both cases is < 10(-7) . Results from wireless recording of the background current of a carbon-fiber microelectrode (CFM) in one fast-scan cyclic voltammetry (FSCV) scan using the IR-UWB link are also included, exhibiting excellent match with those obtained from a conventional frequency-shift-keyed (FSK) link at ~433 MHz.

Wireless gigabit data telemetry for large-scale neural recording

Implantable wireless neural recording from a large ensemble of simultaneously acting neurons is a critical component to thoroughly investigate neural interactions and brain dynamics from freely moving animals. Recent researches have shown the feasibility of simultaneously recording from hundreds of neurons and suggested that the ability of recording a larger number of neurons results in better signal quality. This massive recording inevitably demands a large amount of data transfer. For example, recording 2000 neurons while keeping the signal fidelity ( > 12 bit, > 40 KS/s per neuron) needs approximately a 1-Gb/s data link. Designing a wireless data telemetry system to support such (or higher) data rate while aiming to lower the power consumption of an implantable device imposes a grand challenge on neuroscience community. In this paper, we present a wireless gigabit data telemetry for future large-scale neural recording interface. This telemetry comprises of a pair of low-power gigabit transmitter and receiver operating at 60 GHz, and establishes a short-distance wireless link to transfer the massive amount of neural signals outward from the implanted device. The transmission distance of the received neural signal can be further extended by an externally rendezvous wireless transceiver, which is less power/heat-constraint since it is not at the immediate proximity of the cortex and its radiated signal is not seriously attenuated by the lossy tissue. The gigabit data link has been demonstrated to achieve a high data rate of 6 Gb/s with a bit-error-rate of 10(-12) at a transmission distance of 6 mm, an applicable separation between transmitter and receiver. This high data rate is able to support thousands of recording channels while ensuring a low energy cost per bit of 2.08 pJ/b.