A frequency shaping neural recorder with 3 pF input capacitance and 11 plus 4.5 bits dynamic range

A High Precision, Wide Dynamic Range Closed-Loop Neuromodulation IC With Rapid Stimulation Artifact Recovery

This article presents a high precision, wide dynamic range (DR) closed-loop neuromodulation (CLNM) system that can completely reject stimulation artifacts (SA) and achieve rapid SA recovery. In the recorder, a novel SA quick-blanking scheme is proposed for rail-to-rail SA rejection while minimizing SA recovery time. Besides, a new analog front-end (AFE) architecture based on a frequency-shaping (FS) technique is developed to extend DR intrinsically. In the stimulator, a stimulation driver implemented with a proposed redundant crossfire (RXF) technique is incorporated to improve the effective resolution of the stimulation current. The designed CLNM system is implemented in a 180 nm Bipolar-CMOS-DMOS (BCD) process. Measurement results show that the system is capable of tolerating rail-to-rail (5 V) SA and reducing the SA recovery time from 12 ms to 0.15 ms. The FS recorder extends the DR at low frequencies (LF) to 17.5 bits to enhance tolerance to LF interferences. The proposed stimulator adopting the 4-way RXF topology improves the effective resolution to 12.75 bits without consuming much extra area and power. Animal experiments demonstrate that the designed system can acquire high-fidelity neural signals immediately after stimulation onsets, thus supporting concurrent recording and stimulation.

An MRI Compatible Data Acquisition Device for Rat Brain Recording Inside 16.4T Magnet

Concurrent recording of neural activities and functional magnetic resonance imaging (fMRI) data is useful for studying the neurovascular coupling relationship. This article presents a low-noise, frequency-shaping based neural recorder chip that is insensitive to radio frequency (RF) pulses and gradient echo artifacts under strong magnetic environment. To support simultaneous recording of local field potentials (LFPs), extracellular spikes, and fMRI data, a magnetic resonance imaging (MRI) compatible data acquisition (DAQ) device based on the designed recorder chip is developed with multiple circuit optimization techniques. Bench-top measurement shows that the designed DAQ device has 4.5 μV input-referred noise integrated from 300 Hz to 3000 Hz, which is not greatly affected by electromagnetic interference (EMI) at ultrahigh magnetic field (UMF, 16.4 T). In animal experiments, the designed DAQ device has been demonstrated to be capable of acquiring both the LFPs and extracellular spikes from a rat's brain before, during, and after MRI scanning. Besides, no obvious artifacts are seen from the designed DAQ device at multiple typical MRI scanning modes, and the system recovery time after gradient artifacts is reduced from more than 25 ms to less than 5 ms. The proposed DAQ device architecture based on the frequency-shaping neural recorder chip is MRI compatible and can provide highly competitive performance for concurrent recording of neural activities and fMRI data.

Power-Efficient LFP-Adaptive Dynamic Zoom-and-Track Incremental ΔΣ Front-End for Dual-Band Subcortical Recordings

We report a power-efficient analog front-end integrated circuit (IC) for multi-channel, dual-band subcortical recordings. In order to achieve high-resolution multi-channel recordings with low power consumption, we implemented an incremental ΔΣ ADC (IADC) with a dynamic zoom-and-track scheme. This scheme continuously tracks local field potential (LFP) and adaptively adjusts the input dynamic range (DR) into a zoomed sub-LFP range to resolve tiny action potentials. Thanks to the reduced DR, the oversampling rate of the IADC can be reduced by 64.3% compared to the conventional approach, leading to significant power reduction. In addition, dual-band recording can be easily attained because the scheme continuously tracks LFPs without additional on-chip hardware. A prototype four-channel front-end IC has been fabricated in 180 nm standard CMOS processes. The IADC achieved 11.3-bit ENOB at 6.8 μW, resulting in the best Walden and SNDR FoMs, 107.9 fJ/c-s and 162.1 dB, respectively, among two different comparison groups: the IADCs reported up to date in the state-of-the-art neural recording front-ends; and the recent brain recording ADCs using similar zooming or tracking techniques to this work. The intrinsic dual-band recording feature reduces the post-processing FPGA resources for subcortical signal band separation by >45.8%. The front-end IC with the zoom-and-track IADC showed an NEF of 5.9 with input-referred noise of 8.2 μVrms, sufficient for subcortical recording. The performance of the whole front-end IC was successfully validated through in vivo animal experiments.

A portable, self-contained neuroprosthetic hand with deep learning-based finger control

Objective.Deep learning-based neural decoders have emerged as the prominent approach to enable dexterous and intuitive control of neuroprosthetic hands. Yet few studies have materialized the use of deep learning in clinical settings due to its high computational requirements.Approach.Recent advancements of edge computing devices bring the potential to alleviate this problem. Here we present the implementation of a neuroprosthetic hand with embedded deep learning-based control. The neural decoder is designed based on the recurrent neural network architecture and deployed on the NVIDIA Jetson Nano-a compacted yet powerful edge computing platform for deep learning inference. This enables the implementation of the neuroprosthetic hand as a portable and self-contained unit with real-time control of individual finger movements.Main results.A pilot study with a transradial amputee is conducted to evaluate the proposed system using peripheral nerve signals acquired from implanted intrafascicular microelectrodes. The preliminary experiment results show the system's capabilities of providing robust, high-accuracy (95%-99%) and low-latency (50-120 ms) control of individual finger movements in various laboratory and real-world environments.Conclusion.This work is a technological demonstration of modern edge computing platforms to enable the effective use of deep learning-based neural decoders for neuroprosthesis control as an autonomous system.Significance.The proposed system helps pioneer the deployment of deep neural networks in clinical applications underlying a new class of wearable biomedical devices with embedded artificial intelligence.Clinical trial registration: DExterous Hand Control Through Fascicular Targeting (DEFT). Identifier: NCT02994160.

Deep Learning-Based Approaches for Decoding Motor Intent From Peripheral Nerve Signals

Previous literature shows that deep learning is an effective tool to decode the motor intent from neural signals obtained from different parts of the nervous system. However, deep neural networks are often computationally complex and not feasible to work in real-time. Here we investigate different approaches' advantages and disadvantages to enhance the deep learning-based motor decoding paradigm's efficiency and inform its future implementation in real-time. Our data are recorded from the amputee's residual peripheral nerves. While the primary analysis is offline, the nerve data is cut using a sliding window to create a “pseudo-online” dataset that resembles the conditions in a real-time paradigm. First, a comprehensive collection of feature extraction techniques is applied to reduce the input data dimensionality, which later helps substantially lower the motor decoder's complexity, making it feasible for translation to a real-time paradigm. Next, we investigate two different strategies for deploying deep learning models: a one-step (1S) approach when big input data are available and a two-step (2S) when input data are limited. This research predicts five individual finger movements and four combinations of the fingers. The 1S approach using a recurrent neural network (RNN) to concurrently predict all fingers' trajectories generally gives better prediction results than all the machine learning algorithms that do the same task. This result reaffirms that deep learning is more advantageous than classic machine learning methods for handling a large dataset. However, when training on a smaller input data set in the 2S approach, which includes a classification stage to identify active fingers before predicting their trajectories, machine learning techniques offer a simpler implementation while ensuring comparably good decoding outcomes to the deep learning ones. In the classification step, either machine learning or deep learning models achieve the accuracy and F1 score of 0.99. Thanks to the classification step, in the regression step, both types of models result in a comparable mean squared error (MSE) and variance accounted for (VAF) scores as those of the 1S approach. Our study outlines the trade-offs to inform the future implementation of real-time, low-latency, and high accuracy deep learning-based motor decoder for clinical applications.

A bioelectric neural interface towards intuitive prosthetic control for amputees

OBJECTIVE

While prosthetic hands with independently actuated digits have become commercially available, state-of-the-art human-machine interfaces (HMI) only permit control over a limited set of grasp patterns, which does not enable amputees to experience sufficient improvement in their daily activities to make an active prosthesis useful.

APPROACH

Here we present a technology platform combining fully-integrated bioelectronics, implantable intrafascicular microelectrodes and deep learning-based artificial intelligence (AI) to facilitate this missing bridge by tapping into the intricate motor control signals of peripheral nerves. The bioelectric neural interface includes an ultra-low-noise neural recording system to sense electroneurography (ENG) signals from microelectrode arrays implanted in the residual nerves, and AI models employing the recurrent neural network (RNN) architecture to decode the subject's motor intention.

MAIN RESULTS

A pilot human study has been carried out on a transradial amputee. We demonstrate that the information channel established by the proposed neural interface is sufficient to provide high accuracy control of a prosthetic hand up to 15 degrees of freedom (DOF). The interface is intuitive as it directly maps complex prosthesis movements to the patient's true intention.

SIGNIFICANCE

Our study layouts the foundation towards not only a robust and dexterous control strategy for modern neuroprostheses at a near-natural level approaching that of the able hand, but also an intuitive conduit for connecting human minds and machines through the peripheral neural pathways. (Clinical trial identifier: NCT02994160).

Noise Optimization Techniques for Switched-Capacitor Based Neural Interfaces

This paper presents the noise optimization of a novel switched-capacitor (SC) based neural interface architecture, and its circuit demonstration in a 0.13 [Formula: see text] CMOS process. To reduce thermal noise folding ratio, and suppress kT/C noise, several noise optimization techniques are developed in the proposed architecture. First, one parasitic capacitance suppression scheme is developed to block noise charge transfer from parasitic capacitors to amplifier output. Second, one recording path-splitting scheme is proposed in the input sampling stage to selectively record local field potentials (LFPs), extracellular spikes, or both for reducing input noise floor, and total power consumption. Third, an auto-zero noise cancellation scheme is developed to suppress kT/C noise in the neural amplifier stage. A prototype neural interface chip was fabricated, and also verified in both bench-top, and In-Vivo experiments. Bench-top testings show the input-referred noise of the designed chip is 4.8 [Formula: see text] from 1 [Formula: see text] to 300 [Formula: see text], and 2.3 [Formula: see text] from 300 [Formula: see text] to 8 kHz respectively, and In-Vivo experiments show the peak-to-peak amplitude of the total noise floor including neural activity, electrode interface noise, and the designed chip is only around 20 [Formula: see text]. In comparison with conventional architectures through both circuit measurement and animal experiments, it is well demonstrated that the proposed noise optimization techniques can effectively reduce circuit noise floor, thus extending the application range of switched-capacitor circuits.

A Wide Dynamic Range Neural Data Acquisition System With High-Precision Delta-Sigma ADC and On-Chip EC-PC Spike Processor

A high-performance, wide dynamic range, fully-integrated neural interface is one key component for many advanced bidirectional neuromodulation technologies. In this paper, to complement the previously proposed frequency-shaping amplifier (FSA) and high-precision electrical microstimulator, we will present a proof-of-concept design of a neural data acquisition (DAQ) system that includes a 15-bit, low-power Delta-Sigma analog-to-digital converter (ADC) and a real-time spike processor based on one exponential component-polynomial component (EC-PC) algorithm. High-precision data conversion with low power consumption and small chip area is achieved by employing several techniques, such as opamp-sharing, multi-bit successive approximation (SAR) quantizer, two-step summation, and ultra-low distortion data weighted averaging (DWA). The on-chip EC-PC engine enables low latency, automatic detection, and extraction of spiking activities, thus supporting closed-loop control, real-time data compression and /or neural information decoding. The prototype chip was fabricated in a 0.13  μm CMOS process and verified in both bench-top and In-Vivo experiments. Bench-top measurement results indicate the designed ADC achieves a peak signal-to-noise and distortion ratio (SNDR) of 91.8 dB and a dynamic range of 93.0 dB over a 10 kHz bandwidth, where the total power consumption of the modulator is only 20  μW at 1.0 V supply, corresponding to a figure-of-merit (FOM) of 31.4fJ /conversion-step. In In-Vivo experiments, the proposed DAQ system has been demonstrated to obtain high-quality neural activities from a rat's motor cortex and also greatly reduce recovery time from system saturation due to electrical microstimulation.

A 0.0023 mm 2/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression

This article demonstrates a scalable, time-division multiplexed biopotential recording front-end capable of real-time differential- and common-mode artifact suppression. A delta-encoded recording architecture exploits the power spectral density (PSD) characteristics of Electrocorticography (ECoG) recordings, combining an 8-bit ADC, and an 8-bit DAC to achieve 14 bits of dynamic range. The flexibility of the digital feedback architecture is leveraged to time-division multiplex 64 differential input channels onto a shared mixed-signal front-end, reducing channel area by 2x compared to the state-of-the-art. The feedback DAC used for delta-encoding also serves to cancel differential artifacts with an off-chip adaptive loop. Analysis of this architecture and measured silicon performance of a 65 nm CMOS test-chip implementation, both on the bench and in-vivo, are included with this paper.

A Compact Quad-Shank CMOS Neural Probe With 5,120 Addressable Recording Sites and 384 Fully Differential Parallel Channels

Large-scale in vivo electrophysiology requires tools that enable simultaneous recording of multiple brain regions at single-neuron level. This calls for the design of more compact neural probes that offer even larger arrays of addressable sites and high channel counts. With this aim, we present in this paper a quad-shank approach to integrate as many as 5,120 sites on a single probe. Compact fully-differential recording channels were designed using a single-gain-stage neural amplifier with a 14-bit ADC, achieving a mean input-referred noise of 7.44 μV_rms in the action-potential band and 7.65 μV_rms in the local-field-potential band, a mean total harmonic distortion of 0.17% at 1 kHz and a mean input-referred offset of 169 μV. The probe base incorporates 384 channels with on-chip power management, reference-voltage generation and digital control, thus achieving the highest level of integration in a neural probe and excellent channel-to-channel uniformity. Therefore, no calibration or external circuitry are required to achieve the above-mentioned performance. With a total area of 2.2 × 8.67 mm² and a power consumption of 36.5 mW, the presented probe enables full-system miniaturization for acute or chronic use in small rodents.

Human motor decoding from neural signals: a review

Many people suffer from movement disability due to amputation or neurological diseases. Fortunately, with modern neurotechnology now it is possible to intercept motor control signals at various points along the neural transduction pathway and use that to drive external devices for communication or control. Here we will review the latest developments in human motor decoding. We reviewed the various strategies to decode motor intention from human and their respective advantages and challenges. Neural control signals can be intercepted at various points in the neural signal transduction pathway, including the brain (electroencephalography, electrocorticography, intracortical recordings), the nerves (peripheral nerve recordings) and the muscles (electromyography). We systematically discussed the sites of signal acquisition, available neural features, signal processing techniques and decoding algorithms in each of these potential interception points. Examples of applications and the current state-of-the-art performance were also reviewed. Although great strides have been made in human motor decoding, we are still far away from achieving naturalistic and dexterous control like our native limbs. Concerted efforts from material scientists, electrical engineers, and healthcare professionals are needed to further advance the field and make the technology widely available in clinical use.

A Bidirectional Neuromodulation Technology for Nerve Recording and Stimulation

Electrical nerve recording and stimulation technologies are critically needed to monitor and modulate nerve activity to treat a variety of neurological diseases. However, current neuromodulation technologies presented in the literature or commercially available products cannot support simultaneous recording and stimulation on the same nerve. To solve this problem, a new bidirectional neuromodulation system-on-chip (SoC) is proposed in this paper, which includes a frequency-shaping neural recorder and a fully integrated neural stimulator with charge balancing capability. In addition, auxiliary circuits consisting of power management and data transmission circuits are designed to provide the necessary power supply for the SoC and the bidirectional data communication between the SoC and an external computer via a universal serial bus (USB) interface, respectively. To achieve sufficient low input noise for sensing nerve activity at a sub-10 μV range, several noise reduction techniques are developed in the neural recorder. The designed SoC was fabricated in a 0.18 μm high-voltage Bipolar CMOS DMOS (BCD) process technology that was described in a previous publication and it has been recently tested in animal experiments that demonstrate the proposed SoC is capable of achieving reliable and simultaneous electrical stimulation and recording on the same nerve.

Online Artifact Cancelation in Same-Electrode Neural Stimulation and Recording Using a Combined Hardware and Software Architecture

Advancing studies of neural network dynamics and developments of closed-loop neural interfaces requires the ability to simultaneously stimulate and record the neural cells. Recording adjacent to or at the stimulation site produces artifact signals that are orders of magnitude larger than the neural responses of interest. These signals often saturate the recording amplifier causing distortion or loss of short-latency evoked responses. This paper proposes a method to cancel the artifact in simultaneous neural recording and stimulation on the same electrode. By combining a novel hardware architecture with concurrent software processing, the design achieves neural signal recovery in a wide range of conditions. The proposed system uniquely demonstrates same-electrode stimulation and recording, with neural signal recovery in presence of stimulation artifact 100 dB larger in magnitude than the underlying signals. The system is tested both in vitro and in vivo, during concurrent stimulation and recording on the same electrode. In vivo results in a rodent model are compared to recordings made by a commercial neural amplifier system connected in parallel.

CMOS Ultralow Power Brain Signal Acquisition Front-Ends: Design and Human Testing

Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultralow power, low-noise amplifier arrays and serializers operating in mosfet weak inversion region are presented. To boost the amplifier's gain for a given current budget, cross-coupled-pair active load topology is used in the first stages of these two amplifiers. These two BSA front-ends are fabricated in 130 and 180 nm CMOS processes, occupying 5.45 mm 2 and 0.352 mm 2 of die areas, respectively (excluding pad rings). The CMOS 130-nm amplifier array is comprised of 64 elements, where each amplifier element consumes 0.216 μW from 0.4 V supply, has input-referred noise voltage (IRNoise) of 2.19 μV[Formula: see text] corresponding to a power efficiency factor (PEF) of 11.7, and occupies 0.044 mm 2 of die area. The CMOS 180 nm amplifier array employs 4 elements, where each element consumes 0.69 μW from 0.6 V supply with IRNoise of 2.3 μV[Formula: see text] (corresponding to a PEF of 31.3) and 0.051 mm 2 of die area. Noninvasive electroencephalographic and invasive electrocorticographic signals were recorded real time directly on able-bodied human subjects, showing feasibility of using these analog front-ends for future fully implantable BSA and brain- computer interface systems.

Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 Analog Front End With Reduced ADC Resolution Requirements

Electrocorticography (ECoG) is an important area of research for Brain-Computer Interface (BCI) development. ECoG, along with some other biopotentials, has spectral characteristics that can be exploited for more optimal front-end performance than is achievable with conventional techniques. This paper optimizes noise performance of such a system and discusses an equalization technique that reduces the analog-to-digital converter (ADC) dynamic range requirements and eliminates the need for a variable gain amplifier (VGA). We demonstrate a fabricated prototype in 1p9m 65 nm CMOS that takes advantage of the presented findings to achieve high-fidelity, full-spectrum ECoG recording. It requires 1.08 μW over a 150 Hz bandwidth for the entire analog front end and only 7 bits of ADC resolution.