A 0.45 V 100-channel neural-recording IC with sub- μW/channel consumption in 0.18 μm CMOS

A CMOS BD-BCI: Neural Recorder With Two-Step Time-Domain Quantizer and Multipolar Stimulator With Dual-Mode Charge Balancing

This work presents a bi-directional brain-computer interface (BD-BCI) including a high-dynamic-range (HDR) two-step time-domain neural acquisition (TTNA) system and a high-voltage (HV) multipolar neural stimulation system incorporating dual-mode time-based charge balancing (DTCB) technique. The proposed TTNA includes four independent recording modules that can sense microvolt neural signals while tolerating large stimulation artifacts. In addition, it exhibits an integrated input-referred noise of 2.3 Vrms from 0.1- to 250-Hz and can handle a linear input-signal swing of up to 340 mVPP. The multipolar stimulator is composed of four standalone stimulators each with a maximum current of up to 14 mA (20-V of voltage compliance) and 8-bit resolution. An inter-channel interference cancellation circuitry is introduced to preserve the accuracy and effectiveness of the DTCB method in the multipolar-stimulation configuration. Fabricated in an HV 180-nm CMOS technology, the BD-BCI chipset undergoes extensive in-vitro and in-vivo evaluations. The recording system achieves a measured SNDR, SFDR, and CMRR of 84.8 dB, 89.6 dB, and 105 dB, respectively. The measurement results verify that the stimulation system is capable of performing high-precision charge balancing with 2 mV and 7.5 mV accuracy in the interpulse-bounded time-based charge balancing (TCB) and artifactless TCB modes, respectively.

68-channel neural signal processing system-on-chip with integrated feature extraction, compression, and hardware accelerators for neuroprosthetics in 22 nm FDSOI

Introduction

Multi-channel electrophysiology systems for recording of neuronal activity face significant data throughput limitations, hampering real-time, data-informed experiments. These limitations impact both experimental neurobiology research and next-generation neuroprosthetics.

Methods

We present a novel solution that leverages the high integration density of 22nm fully-depleted silicon-on-insulator technology to address these challenges. The proposed highly integrated programmable System-on-Chip (SoC) comprises 68-channel 0.41 μW/Ch recording frontends, spike detectors, 16-channel 0.87-4.39 μW/Ch action potentials and 8-channel 0.32 μW/Ch local field potential codecs, as well as a multiply-accumulate-assisted power-efficient processor operating at 25 MHz (5.19 μW/MHz). The system supports on-chip training processes for compression, training, and inference for neural spike sorting. The spike sorting achieves an average accuracy of 91.48 or 94.12% depending on the utilized features. The proposed programmable SoC is optimized for reduced area (9 mm2) and power. On-chip processing and compression capabilities free up the data bottlenecks in data transmission (up to 91% space saving ratio), and moreover enable a fully autonomous yet flexible processor-driven operation.

Discussion

Combined, these design considerations overcome data-bottlenecks by allowing on-chip feature extraction and subsequent compression.

Wearable super-resolution muscle-machine interfacing

Muscles are the actuators of all human actions, from daily work and life to communication and expression of emotions. Myography records the signals from muscle activities as an interface between machine hardware and human wetware, granting direct and natural control of our electronic peripherals. Regardless of the significant progression as of late, the conventional myographic sensors are still incapable of achieving the desired high-resolution and non-invasive recording. This paper presents a critical review of state-of-the-art wearable sensing technologies that measure deeper muscle activity with high spatial resolution, so-called super-resolution. This paper classifies these myographic sensors according to the different signal types (i.e., biomechanical, biochemical, and bioelectrical) they record during measuring muscle activity. By describing the characteristics and current developments with advantages and limitations of each myographic sensor, their capabilities are investigated as a super-resolution myography technique, including: (i) non-invasive and high-density designs of the sensing units and their vulnerability to interferences, (ii) limit-of-detection to register the activity of deep muscles. Finally, this paper concludes with new opportunities in this fast-growing super-resolution myography field and proposes promising future research directions. These advances will enable next-generation muscle-machine interfaces to meet the practical design needs in real-life for healthcare technologies, assistive/rehabilitation robotics, and human augmentation with extended reality.

A PVT-Robust AFE-Embedded Error-Feedback Noise-Shaping SAR ADC With Chopper-Based Passive High-Pass IIR Filtering for Direct Neural Recording

This paper presents a PVT-robust error-feedback (EF) noise-shaping SAR (NS-SAR) ADC for direct neural-signal recording. For closed-loop bidirectional neural interfaces enabling the next generation neurological devices, a wide-dynamic-range neural recording circuit is required to accommodate stimulation artifacts. A recording structure using an NS-SAR ADC can be a good candidate because the high resolution and wide dynamic range can be obtained with a low oversampling ratio and power consumption. However, NS-SAR ADCs require an additional gain stage to obtain a well-shaped noise transfer function (NTF), and a dynamic amplifier is often used as the gain stage to minimize power overhead at the cost of vulnerability to PVT variations. To overcome this limitation, the proposed work reutilizes the capacitive-feedback amplifier, which is the analog front-end of the neural recording circuit, as a PVT-robust gain stage to achieve a reliable NS performance. In addition, a new chopper-based implementation of a passive high-pass IIR filter is proposed, achieving an improved NTF compared to prior EF NS-SAR ADCs. Fabricated in a 180-nm CMOS process, the proposed NS-SAR ADC consumes 4.3-μW power and achieves a signal-to-noise-and-distortion ratio (SNDR) of 71.7 dB and 82.7 dB for a bandwidth of 5 kHz and 300 Hz, resulting in a Schreier figure of merit (FOM) of 162.4 dB and 162.1 dB, respectively. Direct neural recording using the proposed NS-SAR ADC is demonstrated successfully in vivo, and also its tolerance against stimulation artifacts is validated in vitro.

Flexible Pressure Sensor Array with Multi-Channel Wireless Readout Chip

Flexible sensor arrays are widely used for wearable physiological signal recording applications. A high density sensor array requires the signal readout to be compatible with multiple channels. This paper presents a highly-integrated remote health monitoring system integrating a flexible pressure sensor array with a multi-channel wireless readout chip. The custom-designed chip features 64 voltage readout channels, a power management unit, and a wireless transceiver. The whole chip fabricated in a 65 nm complementary metal-oxide-semiconductor (CMOS) process occupies 3.7 × 3.7 mm², and the core blocks consume 2.3 mW from a 1 V supply in the wireless recording mode. The proposed multi-channel system is validated by measuring the ballistocardiogram (BCG) and pulse wave, which paves the way for future portable remote human physiological signals monitoring devices.

A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific research and medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip real-time data processing and training for neural signal analysis. It consists of a digitally-assisted 16-channel analog front-end with 1.52 μW/Ch, dedicated bio-processing accelerators for spike detection and classification with 2.79 μW/Ch, and a 125 MHz RISC-V CPU, utilizing adaptive body biasing at 0.5 V with a supporting 1.79 TOPS/W MAC array. The proposed SoC shows a proof-of-concept of how to realize a high-level integration of various on-chip accelerators to satisfy the neural probe requirements for modern applications.

A Fully-Integrated 1µW/Channel Dual-Mode Neural Data Acquisition System for Implantable Brain-Machine Interfaces

This paper presents an ultra-low power mixed-signal neural data acquisition (MSN-DAQ) system that enables a novel low-power hybrid-domain neural decoding architecture for implantable brain-machine interfaces with high channel count. Implemented in 180nm CMOS technology, the 32-channel custom chip operates at 1V supply voltage and achieves excellent performance including 1.07µW/channel, 2.37/5.62 NEF/PEF and 88dB common-mode rejection ratio (CMRR) with significant back-end power-saving advantage compared to prior works. The fabricated prototype was further evaluated with in vivo human tests at bedside, and its performance closely follows that of a commercial recording system.

A 1024-Channel 10-Bit 36- μW/ch CMOS ROIC for Multiplexed GFET-Only Sensor Arrays in Brain Mapping

This paper presents a 1024-channel neural read-out integrated circuit (ROIC) for solution-gated GFET sensing probes in massive μECoG brain mapping. The proposed time-domain multiplexing of GFET-only arrays enables low-cost and scalable hybrid headstages. Low-power CMOS circuits are presented for the GFET analog frontend, including a CDS mechanism to improve preamplifier noise figures and 10-bit 10-kS/s A/D conversion. The 1024-channel ROIC has been fabricated in a standard 1.8-V 0.18- μm CMOS technology with 0.012 mm ² and 36 μ W per channel. An automated methodology for the in-situ calibration of each GFET sensor is also proposed. Experimental ROIC tests are reported using a custom FPGA-based μECoG headstage with 16×32 and 32×32 GFET probes in saline solution and agar substrate. Compared to state-of-art neural ROICs, this work achieves the largest scalability in hybrid platforms and it allows the recording of infra-slow neural signals.

A Miniaturized 256-Channel Neural Recording Interface with Area-Efficient Hybrid Integration of Flexible Probes and CMOS Integrated Circuits

We report a miniaturized, minimally invasive high-density neural recording interface that occupies only a 1.53 mm2 footprint for hybrid integration of a flexible probe and a 256-channel integrated circuit chip. To achieve such a compact form factor, we developed a custom flip-chip bonding technique using anisotropic conductive film and analog circuit-under-pad in a tiny pitch of 75 m. To enhance signal-to-noise ratios, we applied a reference-replica topology that can provide the matched input impedance for signal and reference paths in low-noise aimpliers (LNAs). The analog front-end (AFE) consists of LNAs, buffers, programmable gain amplifiers, 10b ADCs, a reference generator, a digital controller, and serial-peripheral interfaces (SPIs). The AFE consumes 51.92 W from 1.2 V and 1.8 V supplies in an area of 0.0161 mm2 per channel, implemented in a 180 nm CMOS process. The AFE shows > 60 dB mid-band CMRR, 6.32 Vrms input-referred noise from 0.5 Hz to 10 kHz, and 48 M input impedance at 1 kHz. The fabricated AFE chip was directly flip-chip bonded with a 256-channel flexible polyimide neural probe and assembled in a tiny head-stage PCB. Full functionalities of the fabricated 256-channel interface were validated in both in vitro and in vivo experiments, demonstrating the presented hybrid neural recording interface is suitable for various neuroscience studies in the quest of large scale, miniaturized recording systems.

Energy-Efficient Integrated Circuit Solutions Toward Miniaturized Closed-Loop Neural Interface Systems

Miniaturized implantable devices play a crucial role in neural interfaces by monitoring and modulating neural activities on the peripheral and central nervous systems. Research efforts toward a compact wireless closed-loop system stimulating the nerve automatically according to the user's condition have been maintained. These systems have several advantages over open-loop stimulation systems such as reduction in both power consumption and side effects of continuous stimulation. Furthermore, a compact and wireless device consuming low energy alleviates foreign body reactions and risk of frequent surgical operations. Unfortunately, however, the miniaturized closed-loop neural interface system induces several hardware design challenges such as neural activity recording with severe stimulation artifact, real-time stimulation artifact removal, and energy-efficient wireless power delivery. Here, we will review recent approaches toward the miniaturized closed-loop neural interface system with integrated circuit (IC) techniques.

Analysis and Reduction of Nonlinear Distortion in AC-Coupled CMOS Neural Amplifiers with Tunable Cutoff Frequencies

Integrated CMOS neural amplifiers are key elements of modern large-scale neuroelectronic interfaces. The neural amplifiers are routinely AC-coupled to electrodes to remove the DC voltage. The large resistances required for the AC coupling circuit are usually realized using MOSFETs that are nonlinear. Specifically, designs with tunable cutoff frequency of the input high‑pass filter may suffer from excessive nonlinearity, since the gate-source voltages of the transistors forming the pseudoresistors vary following the signal being amplified. Consequently, the nonlinear distortion in such circuits may be high for signal frequencies close to the cutoff frequency of the input filter. Here we propose a simple modification of the architecture of a tunable AC-coupled amplifier, in which the bias voltages V_gs of the transistors forming the pseudoresistor are kept constant independently of the signal levels, what results in significantly improved linearity. Based on numerical simulations of the proposed circuit designed in 180 nm technology we analyze the Total Harmonic Distortion levels as a function of signal frequency and amplitude. We also investigate the impact of basic amplifier parameters—gain, cutoff frequency of the AC coupling circuit, and silicon area—on the distortion and noise performance. The post-layout simulations of the complete test ASIC show that the distortion is very significantly reduced at frequencies near the cutoff frequency, when compared to the commonly used circuits. The THD values are below 1.17% for signal frequencies 1 Hz–10 kHz and signal amplitudes up to 10 mV peak-to-peak. The preamplifier area is only 0.0046 mm² and the noise is 8.3 µV_rms in the 1 Hz–10 kHz range. To our knowledge this is the first report on a CMOS neural amplifier with systematic characterization of THD across complete range of frequencies and amplitudes of neuronal signals recorded by extracellular electrodes.

Lossless Compression of Intracortical Extracellular Neural Recordings using Non-Adaptive Huffman Encoding

This paper investigates the effectiveness of four Huffman-based compression schemes for different intracortical neural signals and sample resolutions. The motivation is to find effective lossless, low-complexity data compression schemes for Wireless Intracortical Brain-Machine Interfaces (WI-BMI). The considered schemes include pre-trained Lone 1^st and 2^nd order encoding [1], pre-trained Delta encoding, and pre-trained Linear Neural Network Time (LNNT) encoding [2]. Maximum codeword-length limited versions are also considered to protect against overfit to training data. The considered signals are the Extracellular Action Potential signal, the Entire Spiking Activity signal, and the Local Field Potential signal. Sample resolutions of 5 to 13 bits are considered. The result show that overfit-protection dramatically improves compression, especially at higher sample resolutions. Across signals, 2^nd order encoding generally performed best at lower sample resolutions, and 1^st order, Delta and LNNT encoding performed best at higher sample resolutions. The proposed methods should generalise to other remote sensing applications where the distribution of the sensed data can be estimated a priori.

A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS

This paper presents an 8-channel energy-efficient analog front-end (AFE) for neural recording, with improvements in power supply rejection ratio (PSRR) and dynamic range. The input stage in the low noise amplifier (LNA) adopts low voltage supply (0.35 V) and current-reusing to achieve ultralow power. To maintain a high PSRR performance while using such a low-voltage supply, a replica-biasing scheme is proposed to generate a stable bias current for the input stage of the LNA despite large supply interference. By exploiting the signal characteristics in the tetrode recording, an averaged local field potential (A-LFP) servo loop is introduced to extend the dynamic range without consuming too much extra power and chip area. The A-LFP signal is generated by integrating the four-channel PGA outputs from the same tetrode. Furthermore, the outputs of the programmable gain amplifier (PGA) are level shifted to bias the input nodes of the amplifier through large pseudo resistors, thus increase the maximum output range without distortion under the low-voltage supply. The proof-of-concept prototype is fabricated in a 65 nm CMOS process. Each recording channel including an LNA and a PGA occupies 0.04 mm ² and consumes 340 nW from the 0.35 V and 0.7 V supply. Each A-LFP servo loop, which is shared by four recording channels, occupies 0.04 mm ² and consumes 190 nW. The maximum gain of the AFE is 54 dB, and the input-referred noise is 6.7 μV over the passband from 0.5 Hz to 6.5 kHz. Measurement also shows that the 0.35 V replica-biasing input stage can tolerate a large interferer up to 200 mVpp with a PSRR of 74 dB, which has been improved to 110 dB with a silicon respin that shields critical wires in the layout.

A Novel General Purpose Combined DFVF/VCII Based Biomedical Amplifier

We here present a 0.15 µm CMOS high input impedance and low noise AC coupled flipped voltage follower-based amplifier for high integration level in integrated circuits in a wide range of sensing applications. With such a circuit, it is possible to achieve a high level of integration, thanks to the absence of passive resistors, and also to implement a very high input impedance without capacitive feedback thanks to bootstrap operation, thus offering a very low high-pass cutoff frequency. Simulated results with a proven and well modeled standard technology show a whole circuit input-referred noise of 5.4 µVrms. The bias voltage is ±0.6 V with a total power consumption of the single amplifier of 20 µW. The very low circuit complexity allows a very low estimated reduced area occupation giving, as a general example, the possibility of integrating an array of up to thousands of channels for biomedical applications. Detailed simulation results, PVT analysis and comparison tables are also presented in the paper.

Human motor decoding from neural signals: a review

Many people suffer from movement disability due to amputation or neurological diseases. Fortunately, with modern neurotechnology now it is possible to intercept motor control signals at various points along the neural transduction pathway and use that to drive external devices for communication or control. Here we will review the latest developments in human motor decoding. We reviewed the various strategies to decode motor intention from human and their respective advantages and challenges. Neural control signals can be intercepted at various points in the neural signal transduction pathway, including the brain (electroencephalography, electrocorticography, intracortical recordings), the nerves (peripheral nerve recordings) and the muscles (electromyography). We systematically discussed the sites of signal acquisition, available neural features, signal processing techniques and decoding algorithms in each of these potential interception points. Examples of applications and the current state-of-the-art performance were also reviewed. Although great strides have been made in human motor decoding, we are still far away from achieving naturalistic and dexterous control like our native limbs. Concerted efforts from material scientists, electrical engineers, and healthcare professionals are needed to further advance the field and make the technology widely available in clinical use.

A Sub- μW/Ch Analog Front-End for ∆-Neural Recording With Spike-Driven Data Compression

We present a fully implantable neural recording IC with a spike-driven data compression scheme to improve the power efficiency and preserve crucial data for monitoring brain activities. A difference between two consecutive neural signals, ∆-neural signal, is sampled in each channel to reduce the full dynamic range and the required resolution of an analog-to-digital converter (ADC), enabling the whole analog chain to be operated at a 0.5-V supply. A set of multiple ∆-signals are stored in analog memory to extract the magnitude and frequency features of the incoming neural signals, which are utilized to discriminate spikes in these signals instantaneously after the acquisition in the analog domain. The energy- and area-efficient successive approximation ADC is implemented and only converts detected spikes, decreasing the power dissipation and the amount of neural data. A prototype 16-channel neural interface IC was fabricated using a 0.18-μm CMOS process, and each component in the analog front-end was fully characterized. We successfully demonstrated precise spike detection through both in vitro and in vivo acquisition of the neural signal. The prototype chip consumed 0.88 μW/channel at a 0.5-V supply for the recording and compressed about 89% of neural data, saving the power consumption and bandwidth in the system.

Acquisition of Neural Action Potentials Using Rapid Multiplexing Directly at the Electrodes

Neural recording systems that interface with implanted microelectrodes are used extensively in experimental neuroscience and neural engineering research. Interface electronics that are needed to amplify, filter, and digitize signals from multichannel electrode arrays are a critical bottleneck to scaling such systems. This paper presents the design and testing of an electronic architecture for intracortical neural recording that drastically reduces the size per channel by rapidly multiplexing many electrodes to a single circuit. The architecture utilizes mixed-signal feedback to cancel electrode offsets, windowed integration sampling to reduce aliased high-frequency noise, and a successive approximation analog-to-digital converter with small capacitance and asynchronous control. Results are presented from a 180 nm CMOS integrated circuit prototype verified using in vivo experiments with a tungsten microwire array implanted in rodent cortex. The integrated circuit prototype achieves <0.004 mm² area per channel, 7 µW power dissipation per channel, 5.6 µVrms input referred noise, 50 dB common mode rejection ratio, and generates 9-bit samples at 30 kHz per channel by multiplexing at 600 kHz. General considerations are discussed for rapid time domain multiplexing of high-impedance microelectrodes. Overall, this work describes a promising path forward for scaling neural recording systems to numbers of electrodes that are orders of magnitude larger.

0.6 V, 116 nW Neural Spike Acquisition IC with Self-Biased Instrumentation Amplifier and Analog Spike Extraction

This paper presents an ultralow power 0.6 V 116 nW neural spike acquisition integrated circuit with analog spike extraction. To reduce power consumption, an ultralow power self-biased current-balanced instrumentation amplifier (IA) is proposed. The passive RC lowpass filter in the amplifier acts as both DC servo loop and self-bias circuit. The spike detector, based on an analog nonlinear energy operator consisting of a low-voltage open-loop differentiator and an open-loop gate-bulk input multiplier, is designed to emphasize the high frequency spike components nonlinearly. To reduce the spike detection error, the adjacent spike merger is also proposed. The proposed circuit achieves a low IA current consumption of 46.4 nA at 0.6 V, noise efficiency factor (NEF) of 1.81, the bandwidth from 102 Hz to 1.94 kHz, the input referred noise of 9.37 μVrms, and overall power consumption of 116 nW at 0.6 V. The proposed circuit can be used in the ultralow power spike pulses acquisition applications, including the neurofeedback systems on peripheral nerves with low neuron density.

Current-Efficient Preamplifier Architecture for CMRR Sensitive Neural Recording Applications

There are neural recording applications in which the amplitude of common-mode interfering signals is several orders of magnitude higher than the amplitude of the signals of interest. This challenging situation for neural amplifiers occurs, among other applications, in neural recordings of weakly electric fish or nerve activity recordings made with cuff electrodes. This paper reports an integrated neural amplifier architecture targeting in-vivo recording of local field potentials and unitary signals from the brain stem of a weakly electric fish Gymnotus omarorum. The proposed architecture offers low noise, high common-mode rejection ratio (CMRR), current-efficiency, and a high-pass frequency fixed without MOS pseudoresistors. The main contributions of this work are the overall architecture coupled with an efficient and simple single-stage circuit for the amplifier main transconductor, and the ability of the amplifier to acquire biopotential signals from high-amplitude common-mode interference in an unshielded environment. A fully-integrated neural preamplifier, which performs well in line with the state-of-the-art of the field while providing enhanced CMRR performance, was fabricated in a 0.5  m CMOS process. Results from measurements show that the gain is 49.5 dB, the bandwidth ranges from 13 Hz to 9.8 kHz, the equivalent input noise is 1.88  V, the CMRR is 87 dB and the Noise Efficiency Factor is 2.1. In addition, in-vivo recordings of weakly electric fish neural activity performed by the proposed amplifier are introduced and favorably compared with those of a commercial laboratory instrumentation system.

A Time-Domain Analog Spatial Compressed Sensing Encoder for Multi-Channel Neural Recording

A time-domain analog spatial compressed sensing encoder for neural recording applications is proposed. Owing to the advantage of MEMS technologies, the number of channels on a silicon neural probe array has doubled in 7.4 years, and therefore, a greater number of recording channels and higher density of front-end circuitry is required. Since neural signals such as action potential (AP) have wider signal bandwidth than that of an image sensor, a data compression technique is essentially required for arrayed neural recording systems. In this paper, compressed sensing (CS) is employed for data reduction, and a novel time-domain analog CS encoder is proposed. A simpler and lower power circuit than conventional analog or digital CS encoders can be realized by using the proposed CS encoder. A prototype of the proposed encoder was fabricated in a 180 nm 1P6M CMOS process, and it achieved an active area of 0.0342 mm 2 / ch . and an energy efficiency of 25.0 pJ / ch . · conv .

Feasibility Study on Active Back Telemetry and Power Transmission Through an Inductive Link for Millimeter-Sized Biomedical Implants

This paper presents a feasibility study of wireless power and data transmission through an inductive link to a 1-mm ² implant, to be used as a free-floating neural probe, distributed across a brain area of interest. The proposed structure utilizes a four-coil inductive link for back telemetry, shared with a three-coil link for wireless power transmission. We propose a design procedure for geometrical optimization of the inductive link in terms of power transmission efficiency (PTE) considering specific absorption rate and data rate. We have designed a low-power pulse-based active data transmission circuit and characterized performance of the proposed inductive link in terms of its data rate and bit error rate (BER). The 1-mm² data-Tx/power-Rx coil is implemented using insulated bonding wire with diameter, resulting in measured PTE in tissue media of 2.01% at 131 MHz and 1.8-cm coil separation distance when the resonator coil inner radius is 1 cm. The measured BER at 1-Mbps data rate was and in the air and tissue environments, respectively.

Time Multiplexed Active Neural Probe with 1356 Parallel Recording Sites

We present a high electrode density and high channel count CMOS (complementary metal-oxide-semiconductor) active neural probe containing 1344 neuron sized recording pixels (20 µm × 20 µm) and 12 reference pixels (20 µm × 80 µm), densely packed on a 50 µm thick, 100 µm wide, and 8 mm long shank. The active electrodes or pixels consist of dedicated in-situ circuits for signal source amplification, which are directly located under each electrode. The probe supports the simultaneous recording of all 1356 electrodes with sufficient signal to noise ratio for typical neuroscience applications. For enhanced performance, further noise reduction can be achieved while using half of the electrodes (678). Both of these numbers considerably surpass the state-of-the art active neural probes in both electrode count and number of recording channels. The measured input referred noise in the action potential band is 12.4 µVrms, while using 678 electrodes, with just 3 µW power dissipation per pixel and 45 µW per read-out channel (including data transmission).

A Neural Probe With Up to 966 Electrodes and Up to 384 Configurable Channels in 0.13 $\mu$m SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13- μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20  μm thick), achieving a crosstalk of [Formula: see text] dB. The probe base (5 × 9 mm ² ) implements dual-band recording and a 171.6 Mbps digital interface. Measurement results show a total input-referred noise of 6.4 μ V _rms and a total power consumption of 49.1  μW/channel.

System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor

This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

A Neuromorphic Event-Based Neural Recording System for Smart Brain-Machine-Interfaces

Neural recording systems are a central component of Brain-Machince Interfaces (BMIs). In most of these systems the emphasis is on faithful reproduction and transmission of the recorded signal to remote systems for further processing or data analysis. Here we follow an alternative approach: we propose a neural recording system that can be directly interfaced locally to neuromorphic spiking neural processing circuits for compressing the large amounts of data recorded, carrying out signal processing and neural computation to extract relevant information, and transmitting only the low-bandwidth outcome of the processing to remote computing or actuating modules. The fabricated system includes a low-noise amplifier, a delta-modulator analog-to-digital converter, and a low-power band-pass filter. The bio-amplifier has a programmable gain of 45-54 dB, with a Root Mean Squared (RMS) input-referred noise level of 2.1 μV, and consumes 90 μW . The band-pass filter and delta-modulator circuits include asynchronous handshaking interface logic compatible with event-based communication protocols. We describe the properties of the neural recording circuits, validating them with experimental measurements, and present system-level application examples, by interfacing these circuits to a reconfigurable neuromorphic processor comprising an array of spiking neurons with plastic and dynamic synapses. The pool of neurons within the neuromorphic processor was configured to implement a recurrent neural network, and to process the events generated by the neural recording system in order to carry out pattern recognition.

A Low-Voltage Chopper-Stabilized Amplifier for Fetal ECG Monitoring With a 1.41 Power Efficiency Factor

This paper presents a low-voltage current-reuse chopper-stabilized frontend amplifier for fetal ECG monitoring. The proposed amplifier allows for individual tuning of the noise in each measurement channel, minimizing the total power consumption while satisfying all application requirements. The low-voltage current reuse topology exploits power optimization in both the current and the voltage domain, exploiting multiple supply voltages (0.3, 0.6 and 1.2 V). The power management circuitry providing the different supplies is optimized for high efficiency (peak charge-pump efficiency = 90%).The low-voltage amplifier together with its power management circuitry is implemented in a standard 0.18 μm CMOS process and characterized experimentally. The amplifier core achieves both good noise efficiency factor (NEF=1.74) and power efficiency factor (PEF=1.05). Experiments show that the amplifier core can provide a noise level of 0.34 μVrms in a 0.7 to 182 Hz band, consuming 1.17 μW power. The amplifier together with its power management circuitry consumes 1.56 μW, achieving a PEF of 1.41. The amplifier is also validated with adult ECG and pre-recorded fetal ECG measurements.

An ECG recording front-end with continuous-time level-crossing sampling

An ECG recording front-end with a continuous- time asynchronous level-crossing analog-to-digital converter (LC-ADC) is proposed. The system is a voltage and current mixed-mode system, which comprises a low noise amplifier (LNA), a programmable voltage-to-current converter (PVCC) as a programmable gain amplifier (PGA) and an LC-ADC with calibration DACs and an RC oscillator. The LNA shows an input referred noise of 3.77 μVrms over 0.06 Hz-950 Hz bandwidth. The total harmonic distortion (THD) of the LNA is 0.15% for a 10 mVPP input. The ECG front-end consumes 8.49 μW from a 1 V supply and achieves an ENOB up to 8 bits. The core area of the proposed front-end is 690 ×710 μm2, fabricated in a 0.18 μm CMOS technology.

A digitally assisted, signal folding neural recording amplifier

A novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/f(n) characteristics of neural signals is described in this paper. The amplified output is 'folded' into a predefined range of voltages by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm can be applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range. It also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, lower harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a behavioral model to provide a quick estimate of the post reconstruction dynamic range. Measurement results from two different core amplifier designs in 65 nm and 180 nm CMOS processes are presented to prove the generality of the proposed scheme in the neural recording applications. Operating from a 1 V power supply, the amplifier in 180 nm CMOS has a gain of 54.2 dB, bandwidth of 5.7 kHz, input referred noise of 3.8 μVrms and power dissipation of 2.52 μW leading to a NEF of 3.1 in spike band. It exhibits a dynamic range of 66 dB and maximum SNDR of 43 dB in LFP band. It also reduces system level power (by reducing the number of bits in the ADC by 2) as well as data rate to 80% of a conventional design. In vivo measurements validate the ability of this amplifier to simultaneously record spike and LFP signals.