Current-Efficient Preamplifier Architecture for CMRR Sensitive Neural Recording Applications

A High CMRR Differential Difference Amplifier Employing Combined Input Pairs for Neural Signal Recordings

This article introduces a Combined .symmetrical and complementary Input Pairs (CIP) of a Differential Difference Amplifier (DDA), to boost the total Common-Mode Rejection Ratio (CMRR) for multi-channel neural signal recording. The proposed CIP-DDA employs three input pairs (transconductors). The dc-coupled input neural signal connection, via the gate terminal of the first transconductor, yields a high input impedance. The high-pass corner frequency and dc quiescent operation point are stabilized by the second transconductor. The calibration path of differential-mode gain and Common-Mode Feedback (CMFB) is provided by the proposed third transconductor. The parallel connection has no need for extra voltage headroom of input and output. The proposed CIP-DDA is targeted at integrated circuit realization and designed in a 0.18-μm CMOS technology. The proposed CIP-DDAs with system CMFB achieve an average CMRR of 103 dB, and each channel consumes circa 3.6 μW power consumption.

Design of a 0.5 V Chopper-Stabilized Differential Difference Amplifier for Analog Signal Processing Applications

This paper presents a low-voltage low-power chopper-stabilized differential difference amplifier (DDA) realized using 40 nm CMOS technology. Operating with a supply voltage of 0.5 V, a three-stage DDA has been employed to achieve an open-loop gain of 89 dB, while consuming just 0.74 μW of power. The proposed DDA incorporates feed-forward frequency compensation and a Type II compensator to achieve pole-zero cancellation and damping factor control. The DDA has a unity-gain bandwidth (UGB) of 170 kHz, a phase margin (PM) of 63.98°, and a common-mode rejection ratio (CMRR) of up to 100 dB. This circuit can effectively drive a 50 pF capacitor in parallel with a 300 kΩ resistor. The use of the chopper stabilization technique effectively mitigates the offset and 1/f noise. The chopping frequency of the chopper modulator is 5 kHz. The input noise is 245 nV/sqrt (Hz) at 1 kHz, and the input-referred offset under Monte Carlo cases is only 0.26 mV. Such a low-voltage chopper-stabilized DDA will be very useful for analog signal processing applications. Compared to the reported chopper DDA counterparts, the proposed DDA is regarded as that with one of the lowest supply voltages. The proposed DDA has demonstrated its effectiveness in tradeoff design when dealing with multiple parameters pertaining to power consumption, noise, and bandwidth.

Design, implementation, and preliminary in-vivo assessment of a high-CMRR low-NEF wireless EEG miniaturized platform

This work presents the design, manufacture, test, and preliminary in-vivo assessment of the proof-of-concept of a miniaturized wireless platform for acquiring electroencephalography signals, where the input stage is a high-CMRR current-efficiency custom-made integrated neural preamplifier.Clinical relevance- Small, low-power consumption, wireless, wearable devices for chronically monitoring EEG recordings may contribute to the diagnosis of transient neurological events, the characterization and potential forecasting of epileptic seizures, and provide signals for controlling prosthetic and aid devices.

Design of a low-noise low-voltage amplifier for improved neural signal recording

Design of amplifier circuits with low-noise operable at low-power to be used, especially for implantable neural interfaces, remains a huge challenge. This research paper presents the design of a low-noise low-voltage neural recording amplifier suitable for amplifying local field potentials and extracellular action potentials so as to meet the end requirement of an implantable neuro-medical system. Critical performance parameters of the smaller circuit blocks of the complete neural amplifier architecture have been found with the help of detailed mathematical analysis and then verified by the simulations conducted using 0.18 µm 4M1P foundry Semi-conductor Laboratory N-well process. The neural amplifier design proposed in this paper passes neural signal of interest with a mid-band gain of 49.9 dB over a bandwidth of 5.3 Hz-8.6 kHz, draws only 11.5 µW of power from ±0.9 V supply voltage, and exhibits an input-referred noise of 2.6 µV_rms with a noise efficiency factor of 2.27. The area consumed by the proposed neural amplifier architecture is 0.192 mm². The complete circuit design carried out in this paper should prove to be useful in equipment for the diagnosis of neurological disorders.

A Review on VCII Applications in Signal Conditioning for Sensors and Bioelectrical Signals: New Opportunities

This study reviews second-generation voltage conveyor (VCII)-based read-out circuits for sensors and bioelectrical signal conditioning from existing literature. VCII is the dual circuit of a second-generation current conveyor (CCII), which provides the possibility of processing signals in the current domain while providing output signals in the voltage form. The scope of this paper is to discuss the benefits and opportunities of new VCII-based read-out circuits over traditional ones and bioelectrical signals. The achieved main benefits compared to conventional circuits are the simpler read-out circuits, producing an output signal in a voltage form that can be directly used, improved accuracy, possibility of gain adjustment using a single grounded resistor, and the possibility of connecting several SiPM sensors to the readout circuit. The circuits studied in this paper include VCII- based read-out circuits suitable for all types of sensors configured in the current-mode Wheatstone bridge (CMWB) topology, the VCII-based read-out circuits solutions reported for silicon photomultiplier, spiral-shaped ultrasonic PVDF and differential capacitive sensors, and, finally, a simple readout circuitry for sensing bioelectrical signals. There are still not many VCII-based readout circuits, and we hope that the outcome of this study will enhance this area of research and inspire new ideas.

Development on Linearizing Front End and Amplification Structure for Commercial GMR Sensor-based Cardiorespiratory Monitoring system

Magnetoplethysmogram (MPG) is typically acquired by placing a giant magnetoresistance sensor (GMR)-magnet system in a blood vessel's (e.g., radial artery) vicinity. This brief analyzed multiple linearizing front ends for the GMR-magnet system. GMR based analog front end's (AFE) gain requirement is derived through COMSOL and MATLAB-based simulation considering the raw signal data. After that, we designed a fully differential difference amplifier (FDDA) in 0.18 µm, 1.8 V process using the SPICE environment for amplification of MPG signals. An automatic calibration method is used for compensating the GMR sensor's offset and lowering it to a few µV level during constant current excitation. This proposed GMR-magnet system is a stepping stone towards noninvasive arterial pulse waveform (APW) detection using the MPG principle, with or without direct skin contact. The DDA achieves open and closed-loop gain of 102 dB and 32 dB, phase margin of 62^◦, an IRN of 1.8µV, and a unity-gain frequency of 32kHz, resulting in a closed-loop bandwidth of 800 Hz while dissipating 1.2 µA from a 1.8-V supply.

A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer

Modern neuromodulation systems typically provide a large number of recording and stimulation channels, which reduces the available power and area budget per channel. To maintain the necessary input-referred noise performance despite growingly rigorous area constraints, chopped neural front-ends are often the modality of choice, as chopper-stabilization allows to simultaneously improve (1/f) noise and area consumption. The resulting issue of a drastically reduced input impedance has been addressed in prior art by impedance boosters based on voltage buffers at the input. These buffers precharge the large input capacitors, reduce the charge drawn from the electrodes and effectively boost the input impedance. Offset on these buffers directly translates into charge-transfer to the electrodes, which can accelerate electrode aging. To tackle this issue, a voltage buffer with ultra-low time-averaged offset is proposed, which cancels offset by periodic reconfiguration, thereby minimizing unintended charge transfer. This article explains the background and circuit design in detail and presents measurement results of a prototype implemented in a 180 nm HV CMOS process. The measurements confirm that signal-independent, buffer offset induced charge transfer occurs and can be mitigated by the presented buffer reconfiguration without adversely affecting the operation of the input impedance booster. The presented neural recorder front-end achieves state of the art performance with an area consumption of 0.036 mm², an input referred noise of [Formula: see text] (1 to 200 Hz) and [Formula: see text] (0.2 to 10 kHz), power consumption of 13.7 μW from 1.8 V supply, as well as CMRR and PSRR ≥ 83 dB at 50 Hz.

A Compact Sub-μW CMOS ECG Amplifier With 57.5-MΩ Zin, 2.02 NEF, 8.16 PEF and 83.24-dB CMRR

This paper presents a compact DDA-based fully-differential CMOS instrumentation amplifier dedicated for micro-power ECG monitoring. Only eight transistors are employed to realize a power-efficient current-sharing DDA. A RC network (using MOS pseudo resistors and poly capacitors) forms feedback loops around the DDA creating an ac-only amplification. The proposed amplifier is dc-coupled via gate terminals of the p-channel input transistors. It thus achieves sufficiently high input impedance over the entire ECG frequency range. Fabricated in a 0.35-μm CMOS process, the proposed amplifier occupies 0.0712 mm². It operates from a 2 V dc supply with 336 nA current consumption. Measurements show that the amplifier attains its input impedance of 57.5 MΩ at 150 Hz and achieves 1.54 μV_rms input-referred noise over 0.1-300 Hz. Noise and power efficiency factors are 2.02 and 8.16, respectively. At 50 Hz, the mean CMRR of 83.24 dB is obtained from 11-chip measurement. Experiments performed on a human subject confirm the functionality of the proposed amplifier in a real measurement scenario.

A Novel General Purpose Combined DFVF/VCII Based Biomedical Amplifier

We here present a 0.15 µm CMOS high input impedance and low noise AC coupled flipped voltage follower-based amplifier for high integration level in integrated circuits in a wide range of sensing applications. With such a circuit, it is possible to achieve a high level of integration, thanks to the absence of passive resistors, and also to implement a very high input impedance without capacitive feedback thanks to bootstrap operation, thus offering a very low high-pass cutoff frequency. Simulated results with a proven and well modeled standard technology show a whole circuit input-referred noise of 5.4 µVrms. The bias voltage is ±0.6 V with a total power consumption of the single amplifier of 20 µW. The very low circuit complexity allows a very low estimated reduced area occupation giving, as a general example, the possibility of integrating an array of up to thousands of channels for biomedical applications. Detailed simulation results, PVT analysis and comparison tables are also presented in the paper.

Enhanced ICMR amplifier for high CMRR biopotential recordings

This paper presents an integrated biopotential preamplifier architecture targeting applications that simultaneously require high common-mode rejection ratio (CMRR), low noise, high input common-mode range (ICMR), and current-efficiency (low Noise Efficiency Factor or NEF). A biopotential preamplifier, which performs well in line with the state-of-the-art of the field while providing enhanced ICMR and CMRR performance, was fabricated in a 0.5 μm CMOS process. Results from measurements show that the gain is 47 dB, the bandwidth ranges from 1 Hz to 7.7 kHz, the equivalent input noise is 1.8 μV_rms, the CMRR is 100.5 dB, the ICMR is 1.7 V and the NEF is 3.2.