A Wide Dynamic Range Neural Data Acquisition System With High-Precision Delta-Sigma ADC and On-Chip EC-PC Spike Processor

An MRI Compatible Data Acquisition Device for Rat Brain Recording Inside 16.4T Magnet

Concurrent recording of neural activities and functional magnetic resonance imaging (fMRI) data is useful for studying the neurovascular coupling relationship. This article presents a low-noise, frequency-shaping based neural recorder chip that is insensitive to radio frequency (RF) pulses and gradient echo artifacts under strong magnetic environment. To support simultaneous recording of local field potentials (LFPs), extracellular spikes, and fMRI data, a magnetic resonance imaging (MRI) compatible data acquisition (DAQ) device based on the designed recorder chip is developed with multiple circuit optimization techniques. Bench-top measurement shows that the designed DAQ device has 4.5 μV input-referred noise integrated from 300 Hz to 3000 Hz, which is not greatly affected by electromagnetic interference (EMI) at ultrahigh magnetic field (UMF, 16.4 T). In animal experiments, the designed DAQ device has been demonstrated to be capable of acquiring both the LFPs and extracellular spikes from a rat's brain before, during, and after MRI scanning. Besides, no obvious artifacts are seen from the designed DAQ device at multiple typical MRI scanning modes, and the system recovery time after gradient artifacts is reduced from more than 25 ms to less than 5 ms. The proposed DAQ device architecture based on the frequency-shaping neural recorder chip is MRI compatible and can provide highly competitive performance for concurrent recording of neural activities and fMRI data.

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

The performance of analog-to-digital converters (ADCs) has reached a bottleneck due to the limitations of the manufacturing process and testing environment. Time-interleaved ADC (TIADC) technology can increase the sampling rate without changing the resolution. However, channel mismatch severely degrades the dynamic performance of the TIADC system. For the channel mismatch problem of TIADC, most of the current solutions have preconditions, such as eliminating only some kind of error or increasing the complexity of the hardware. A few methods can estimate multiple errors without changing the hardware circuit. To improve the dynamic performance of the TIADC system, on the basis of an in-depth study of the channel mismatch error of TIADC, according to the system identification theory, an identification model is designed to characterize the frequency characteristics of TIADC. Using the system observation data, the transfer function parameters of the system are recursively estimated. By constructing and verifying the identification model of the TIADC system, and then through the frequency domain correction method, a digital compensation filter is established to complete the error correction of the system. The test results of the four-channel TIADC high-speed data acquisition system show that the actual input and output characteristics of the test system are consistent with the nature of the identification model. The four channels of the TIADC system are provided by four sub-channels of two AD9653 chips, and the highest sampling rate of a single channel is 125MSPS. For sinusoidal input signals from 20 MHz to 150 MHz, the sampling system can achieve a signal-to-noise ratio (SNR) above 56.8 dB and spurious free dynamic range (SFDR) above 69.7 dB. The dynamic performance of the sampling system is nearly equivalent to that of its sub-ADC; the feasibility of the model identification method and the effectiveness of error correction are verified in simulation and experiment.

A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems

This paper presents a 14-b 20-MS/s energy-efficient SAR ADC in 65-nm CMOS technology for portable medical ultrasound systems. To break the limitation of the ADC linearity on the DAC size in a SAR ADC, a background mismatch calibration technique is employed. As a result, the thermal noise will be the major constraint for the DAC size. In addition, a compact noise-reduction technique is proposed to alleviate the adverse impact of the input-referred comparator noise on the effective resolution. Moreover, a 2.5-V on-chip LDO, which serves as the reference generator for the ADC core, is also integrated to guarantee the reference accuracy and to suppress the supply noise. To reduce the capacitive load of the comparator and boost the comparison speed, a low fan-in SAR logic is also designed. With the proposed mismatch calibration technique and the noise-reduction technique activated, measured results indicate that the peak signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) achieve 78.8 dB and 95.4 dB, respectively. At 20 MS/s, the ADC consumes 6.8mW from its 1.2 V/3.3V supplies in total, leading to an SNDR-based Schreier FOM of 170.5 dB at Nyquist. The active area of the ADC is 450 × 540μm².

A Low Power 1024-Channels Spike Detector Using Latch-Based RAM for Real-Time Brain Silicon Interfaces

High-density microelectrode arrays allow the neuroscientist to study a wider neurons population, however, this causes an increase of communication bandwidth. Given the limited resources available for an implantable silicon interface, an on-fly data reduction is mandatory to stay within the power/area constraints. This can be accomplished by implementing a spike detector aiming at sending only the useful information about spikes. We show that the novel non-linear energy operator called ASO in combination with a simple but robust noise estimate, achieves a good trade-off between performance and consumption. The features of the investigated technique make it a good candidate for implantable BMIs. Our proposal is tested both on synthetic and real datasets providing a good sensibility at low SNR. We also provide a 1024-channels VLSI implementation using a Random-Access Memory composed by latches to reduce as much as possible the power consumptions. The final architecture occupies an area of 2.3 mm2, dissipating 3.6 µW per channels. The comparison with the state of art shows that our proposal finds a place among other methods presented in literature, certifying its suitability for BMIs.

A 1024-Channel 10-Bit 36- μW/ch CMOS ROIC for Multiplexed GFET-Only Sensor Arrays in Brain Mapping

This paper presents a 1024-channel neural read-out integrated circuit (ROIC) for solution-gated GFET sensing probes in massive μECoG brain mapping. The proposed time-domain multiplexing of GFET-only arrays enables low-cost and scalable hybrid headstages. Low-power CMOS circuits are presented for the GFET analog frontend, including a CDS mechanism to improve preamplifier noise figures and 10-bit 10-kS/s A/D conversion. The 1024-channel ROIC has been fabricated in a standard 1.8-V 0.18- μm CMOS technology with 0.012 mm ² and 36 μ W per channel. An automated methodology for the in-situ calibration of each GFET sensor is also proposed. Experimental ROIC tests are reported using a custom FPGA-based μECoG headstage with 16×32 and 32×32 GFET probes in saline solution and agar substrate. Compared to state-of-art neural ROICs, this work achieves the largest scalability in hybrid platforms and it allows the recording of infra-slow neural signals.

A 400 mV 160 nW/Ch Compact Energy Efficient ∆Σ Modulator for Multichannel Biopotential Signal Acquisition System

Analog to digitalconverter circuit design for biomedical systems with multiple recording channels presents challenges in high density and very low power consumption. Passive integrator and loop-filter based delta-sigma modulators (DSMs) have been recently reported for ultra-low-power and highly energy-efficient data converters for multi-channel biopotential acquisition. However, these modulators rely on a very high oversampling ratio (OSR) to achieve the target resolution. Higher OSR leads to higher power consumption in the modulator and the digital low-pass and decimation filter succeeding the DSM. We present a low OSR passive integrator-based DSM in this work by relying on a duty-cycled resistor (DCR). DCR enables the realization of large time constants in the already passive loop-filter, with minimal area and overhead power consumption. This leads to design of DSMs that are highly area, power and energy-efficient, suitable for multi-channel biopotential recording systems. We demonstrate a second order, duty-cycled passive integrator based CTDSM in a 65 nm CMOS technology for a 10 kHz biopotential bandwidth. Measurement results show that the fabricated design achieves an SNDR/DR of 56.36/63.1 dB while consuming only 160 nW power with an OSR of 32 and occupies an area of 0.035 mm ² with a state-of-the-art energy efficiency of 14.9 fJ/conv. In-vitro and in-vivo measurements are provided to further demonstrate the operation of the proposed DSM.

Directions of Deep Brain Stimulation for Epilepsy and Parkinson's Disease

BACKGROUND

Deep brain stimulation (DBS) is an effective treatment for movement disorders and neurological/psychiatric disorders. DBS has been approved for the control of Parkinson disease (PD) and epilepsy.

OBJECTIVES

A systematic review and possible future direction of DBS system studies is performed in the open loop and closed-loop configuration on PD and epilepsy.

METHODS

We searched Google Scholar database for DBS system and development. DBS search results were categorized into clinical device and research system from the open-loop and closed-loop perspectives.

RESULTS

We performed literature review for DBS on PD and epilepsy in terms of system development by the open loop and closed-loop configuration. This study described development and trends for DBS in terms of electrode, recording, stimulation, and signal processing. The closed-loop DBS system raised a more attention in recent researches.

CONCLUSION

We overviewed development and progress of DBS. Our results suggest that the closed-loop DBS is important for PD and epilepsy.

A bioelectric neural interface towards intuitive prosthetic control for amputees

OBJECTIVE

While prosthetic hands with independently actuated digits have become commercially available, state-of-the-art human-machine interfaces (HMI) only permit control over a limited set of grasp patterns, which does not enable amputees to experience sufficient improvement in their daily activities to make an active prosthesis useful.

APPROACH

Here we present a technology platform combining fully-integrated bioelectronics, implantable intrafascicular microelectrodes and deep learning-based artificial intelligence (AI) to facilitate this missing bridge by tapping into the intricate motor control signals of peripheral nerves. The bioelectric neural interface includes an ultra-low-noise neural recording system to sense electroneurography (ENG) signals from microelectrode arrays implanted in the residual nerves, and AI models employing the recurrent neural network (RNN) architecture to decode the subject's motor intention.

MAIN RESULTS

A pilot human study has been carried out on a transradial amputee. We demonstrate that the information channel established by the proposed neural interface is sufficient to provide high accuracy control of a prosthetic hand up to 15 degrees of freedom (DOF). The interface is intuitive as it directly maps complex prosthesis movements to the patient's true intention.

SIGNIFICANCE

Our study layouts the foundation towards not only a robust and dexterous control strategy for modern neuroprostheses at a near-natural level approaching that of the able hand, but also an intuitive conduit for connecting human minds and machines through the peripheral neural pathways. (Clinical trial identifier: NCT02994160).