Design of Dual-Mode Stimulus Chip With Built-In High Voltage Generator for Biomedical Applications

A Scalable, Programmable Neural Stimulator for Enhancing Generalizability in Neural Interface Applications

Each application of neurostimulators requires unique stimulation parameter specifications to achieve effective stimulation. Balancing the current magnitude with stimulation resolution, waveform, size, and channel count is challenging, leading to a loss of generalizability across broad neural interfaces. To address this, this paper proposes a highly scalable, programmable neurostimulator with a System-on-Chip (SOC) capable of 32 channels of independent stimulation. The compliance voltage reaches up to ±22.5 V. A pair of 8-bit current-mode DACs support independent waveforms for source and sink operations and feature a user-selectable dual range for low-current intraparenchymal microstimulation with a resolution of 4.31 μA/bit, as well as high current stimulation for spinal cord and DBS applications with a resolution of 48.00 μA/bit, achieving a wide stimulation range of 12.24 mA while maintaining high-resolution biological stimulation. A dedicated communication protocol enables full programmable control of stimulation waveforms, effectively improving the range of stimulation parameters. In vivo electrophysiological experiments successfully validate the functionality of the proposed stimulator. This flexible stimulator architecture aims to enhance its generality across a wide range of neural interfaces and will provide more diverse and refined stimulation strategies.

Energy-Efficient Power Management Interface With Adaptive HV Multimode Stimulation for Power-Sensor Integrated Patch-Type Systems

An energy-efficient power management interface (PMI) with adaptive high-voltage (HV) stimulation capability is presented for patch-type healthcare devices where power management and sensor readout circuits are integrated. For efficient power supply, it proposes a multimode buck converter with an adaptive mode controller, delivering 95.6% peak power conversion efficiency and over 90% efficiency across a wide 4-440 mA output current range. For energy-efficient stimulation, a HV stimulation system is designed to perform mode-adaptive on/off control, where the charge pump (CP) is adopted for periodic power saving. The CP output is adaptively tuned to minimize the stimulator's power waste by utilizing a bio-impedance path in the sensor circuit. The stimulation core supports multimode functionality of current-/voltage-controlled stimulations with monopolar and bipolar modes, providing ten kinds of various stimulation waveform shape. For efficient system operation, battery interface circuits are included to monitor state-of-charge (SOC) conditions, and a device power adjustment scheme is proposed to provide SOC-based maximum 28% power reduced optimal operation of high-resolution and low-power. The power-sensor integrated circuits were fabricated in a 0.18-μm CMOS process, and the proposed schemes were experimentally verified. For system-level feasibility, a patch-type device prototype was manufactured, and both power and bio-signal interfaces were functionally demonstrated.

An Ultrasonic Energy Harvesting IC Providing Adjustable Bias Voltage for Pre-Charged CMUT

Ultrasonic wireless power transmission (WPT) using pre-charged capacitive micromachined ultrasonic transducers (CMUT) is drawing great attention due to the easy integration of CMUT with CMOS techniques. Here, we present an integrated circuit (IC) that interfaces with a pre-charged CMUT device for ultrasonic energy harvesting. We implemented an adaptive high voltage charge pump (HVCP) in the proposed IC, which features low power, overvoltage stress (OVS) robustness, and a wide output range. The ultrasonic energy harvesting IC is fabricated in the 180 nm HV BCD process and occupies a 2 × 2.5 mm² silicon area. The adaptive HVCP offers a 2× - 12× voltage conversion ratio (VCR), thereby providing a wide bias voltage range of 4 V-44 V for the pre-charged CMUT. Moreover, a VCR tunning finite state machine (FSM) implemented in the proposed IC can dynamically adjust the VCR to stabilize the HVCP output (i.e., the pre-charged CMUT bias voltage) to a target voltage in a closed-loop manner. Such a closed-loop control mechanism improves the tolerance of the proposed IC to the received power variation caused by misalignments, amount of transmitted power change, and/or load variation. Besides, the proposed ultrasonic energy harvesting IC has an average power consumption of 35 μW-554 μW corresponding to the HVCP output from 4 V-44 V. The CMUT device with a local surface acoustic intensity of 3.78 mW/mm², which is well below the FDA limit for power flux (7.2 mW/mm²), can deliver sufficient power to the IC.

A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm2. Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode−tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.

Advances in Neural Recording and Stimulation Integrated Circuits

In the past few decades, driven by the increasing demands in the biomedical field aiming to cure neurological diseases and improve the quality of daily lives of the patients, researchers began to take advantage of the semiconductor technology to develop miniaturized and power-efficient chips for implantable applications. The emergence of the integrated circuits for neural prosthesis improves the treatment process of epilepsy, hearing loss, retinal damage, and other neurological diseases, which brings benefits to many patients. However, considering the safety and accuracy in the neural prosthesis process, there are many research directions. In the process of chip design, designers need to carefully analyze various parameters, and investigate different design techniques. This article presents the advances in neural recording and stimulation integrated circuits, including (1) a brief introduction of the basics of neural prosthesis circuits and the repair process in the bionic neural link, (2) a systematic introduction of the basic architecture and the latest technology of neural recording and stimulation integrated circuits, (3) a summary of the key issues of neural recording and stimulation integrated circuits, and (4) a discussion about the considerations of neural recording and stimulation circuit architecture selection and a discussion of future trends. The overview would help the designers to understand the latest performances in many aspects and to meet the design requirements better.