A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning

High-Performance Method and Architecture for Attention Computation in DNN Inference

In recent years, The combination of Attention mechanism and deep learning has a wide range of applications in the field of medical imaging. However, due to its complex computational processes, existing hardware architectures have high resource consumption or low accuracy, and deploying them efficiently to DNN accelerators is a challenge. This paper proposes an online-programmable Attention hardware architecture based on compute-in-memory (CIM) marco, which reduces the complexity of Attention in hardware and improves integration density, energy efficiency, and calculation accuracy. First, the Attention computation process is decomposed into multiple cascaded combinatorial matrix operations to reduce the complexity of its implementation on the hardware side; second, in order to reduce the influence of the non-ideal characteristics of the hardware, an online-programmable CIM architecture is designed to improve calculation accuracy by dynamically adjusting the weights; and lastly, it is verified that the proposed Attention hardware architecture can be applied for the inference of deep neural networks through Spice simulation. Based on the 100nm CMOS process, compared with the traditional Attention hardware architectures, the integrated density and energy efficiency are increased by at least 91.38 times, and latency and computing efficiency are improved by about 12.5 times.

Overview of Memristor-Based Design for Analog Applications

Memristor-based design has gained significant attention in recent years due to its potential to revolutionize various fields such as artificial intelligence, neuromorphic computing, non-volatile memory, signal processing, filtering, and radio frequency design. These emerging devices offer unique advantages such as non-volatile memory, low power consumption, and a high integration density. Their scalability and compatibility with existing fabrication processes make them an attractive option for industry adoption, paving the way for faster and more efficient architecture design. Researchers are actively exploring ways to optimize memristor technology for practical applications to harness its full potential. This includes developing novel materials and structures as well as improving the reliability and performance of memristors in various applications. This paper provides a comprehensive overview of the current advancements in memristor technology and their potential impact on the design of future electronic systems, focusing on its applications in the analog domain. By exploring the latest research and development in this field, researchers can gain valuable insights into how analog memristors can be integrated into their designs to achieve enhanced performance and efficiency. The paper delves into the fundamental principles of memristor technology, exploring its unique characteristics and advantages over traditional electronic components. It discusses the potential impact of memristors and challenges in the analog field of electronics, and highlights the progress made in their integration with existing circuitry, enabling novel functionalities and improved performance. Furthermore, it highlights ongoing research efforts to improve the performance and reliability of memristors, as well as the potential limitations and challenges that need to be addressed for widespread adoption, including variability in performance and reliability.

An FPGA implementation of Bayesian inference with spiking neural networks

Spiking neural networks (SNNs), as brain-inspired neural network models based on spikes, have the advantage of processing information with low complexity and efficient energy consumption. Currently, there is a growing trend to design hardware accelerators for dedicated SNNs to overcome the limitation of running under the traditional von Neumann architecture. Probabilistic sampling is an effective modeling approach for implementing SNNs to simulate the brain to achieve Bayesian inference. However, sampling consumes considerable time. It is highly demanding for specific hardware implementation of SNN sampling models to accelerate inference operations. Hereby, we design a hardware accelerator based on FPGA to speed up the execution of SNN algorithms by parallelization. We use streaming pipelining and array partitioning operations to achieve model operation acceleration with the least possible resource consumption, and combine the Python productivity for Zynq (PYNQ) framework to implement the model migration to the FPGA while increasing the speed of model operations. We verify the functionality and performance of the hardware architecture on the Xilinx Zynq ZCU104. The experimental results show that the hardware accelerator of the SNN sampling model proposed can significantly improve the computing speed while ensuring the accuracy of inference. In addition, Bayesian inference for spiking neural networks through the PYNQ framework can fully optimize the high performance and low power consumption of FPGAs in embedded applications. Taken together, our proposed FPGA implementation of Bayesian inference with SNNs has great potential for a wide range of applications, it can be ideal for implementing complex probabilistic model inference in embedded systems.