Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal–oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications.

Ultrahigh Frequency Ultrasonic Transducers Design with Low Noise Amplifier Integrated Circuit

This paper describes the design of an ultrahigh frequency ultrasound system combined with tightly focused 500 MHz ultrasonic transducers and high frequency wideband low noise amplifier (LNA) integrated circuit (IC) model design. The ultrasonic transducers are designed using Aluminum nitride (AlN) piezoelectric thin film as the piezoelectric element and using silicon lens for focusing. The fabrication and characterization of silicon lens was presented in detail. Finite element simulation was used for transducer design and evaluation. A custom designed LNA circuit is presented for amplifying the ultrasound echo signal with low noise. A Common-source and Common-gate (CS-CG) combination structure with active feedback is adopted for the LNA design so that high gain and wideband performances can be achieved simultaneously. Noise and distortion cancelation mechanisms are also employed in this work to improve the noise figure (NF) and linearity. Designed by using a 0.35 μm complementary metal oxide semiconductor (CMOS) technology, the simulated power gain of the echo signal wideband amplifier is 22.5 dB at 500 MHz with a capacitance load of 1.0 pF. The simulated NF at 500 MHz is 3.62 dB.

A 540-[Formula: see text] Duty Controlled RSSI With Current Reusing Technique for Human Body Communication

An ultra-low-power duty controlled received signal strength indicator (RSSI) is implemented for human body communication (HBC) in 180 nm CMOS technology under 1.5 V supply. The proposed RSSI adopted 3 following key features for low-power consumption; 1) current reusing technique (CR-RSSI) with replica bias circuit and calibration unit, 2) duty controller, and 3) reconfigurable gm-boosting LNA. The CR-RSSI utilizes stacked amplifier-rectifier-cell (AR-cell) to reuse the supply current of each blocks. As a result, the power consumption becomes 540 [Formula: see text] with +/-2 dB accuracy and 75 dB dynamic range. The replica bias circuit and calibration unit are adopted to increase the reliability of CR-RSSI. In addition, the duty controller turns off the RSSI when it is not required, and this function leads 70% power reduction. At last, the gm-boosting reconfigurable LNA can adaptively vary its noise and linearity performance with respect to input signal strength. Fro current reusing technique m this feature, we achieve 62% power reduction in the LNA. Thanks to these schemes, compared to the previous works, we can save 70% of power in RSSI and LNA.

A Low-power CMOS BFSK Transceiver for Health Monitoring Systems

A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of -70dBm and -98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10^-3 at the input powers of -70dBm at 1.2V and -98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW.