A hierarchical graph neuron scheme for real-time pattern recognition

Holographic Graph Neuron: A Bioinspired Architecture for Pattern Processing

In this paper, we propose a new approach to implementing hierarchical graph neuron (HGN), an architecture for memorizing patterns of generic sensor stimuli, through the use of vector symbolic architectures. The adoption of a vector symbolic representation ensures a single-layer design while retaining the existing performance characteristics of HGN. This approach significantly improves the noise resistance of the HGN architecture, and enables a linear (with respect to the number of stored entries) time search for an arbitrary subpattern.

Comparison between analog and digital neural network implementations for range-finding applications

A neural network (NN) was developed in order to increase the distance range of a phase-shift laser range finder and to achieve surface recognition, by using two photoelectrical signals issued from the measurement system. The NN architecture consists of a multilayer perceptron (MLP) with two inputs, three neurons in the hidden layer, and one output. Depending on the application, the NN output has to resolve the ambiguity due to phase-shift measurement by linearizing the inverse of the square law, or to indicate an output voltage corresponding to the tested surface. This embedded system dedicated to optoelectronic measurements was successfully tested with an analog NN, implemented in 0.35- microm complimentary metal-oxide-semiconductor (CMOS) technology, resulting in a threefold increase in the distance range with respect to the one limited by the phase-shift measurement, and by discriminating four types of surfaces (a plastic surface, glossy paper, a painted wall, and a porous surface), at a remote distance between the range finder and the target varying from 0.5 m up to 1.25 m and with a laser beam angle varying between -pi/6 and pi/6 with respect to the target. In this type of application, NN analog implementation provides many advantages, notably use of a small silicon area, low power consumption and no analog-to-digital conversions (ADCs). Nevertheless, digital implementation allows ease of conception and reconfigurability and an embedded weight and bias update. This paper presents the complete measurement system and a comparison between both types of implementation, by developing the advantages and drawbacks relative to each method. An optimized mixed architecture, using both techniques, is then proposed and discussed at the end of the paper.