Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology

CMOS Perceptron for Vesicle Fusion Classification

Edge computing (processing data close to its source) is one of the fastest developing areas of modern electronics and hardware information technology. This paper presents the implementation process of an analog CMOS preprocessor for use in a distributed environment for processing medical data close to the source. The task of the circuit is to analyze signals of vesicle fusion, which is the basis of life processes in multicellular organisms. The functionality of the preprocessor is based on a classifier of full and partial fusions. The preprocessor is dedicated to operate in amperometric systems, and the analyzed signals are data from carbon nanotube electrodes. The accuracy of the classifier is at the level of 93.67%. The implementation was performed in the 65 nm CMOS technology with a 0.3 V power supply. The circuit operates in the weak-inversion mode and is dedicated to be powered by thermal cells of the human energy harvesting class. The maximum power consumption of the circuit equals 416 nW, which makes it possible to use it as an implantable chip. The results can be used, among others, in the diagnosis of precancerous conditions.

Energy Efficient Distance Computing: Application to K-Means Clustering

Distance computation between two input vectors is a widely used computing unit in several pattern recognition, signal processing and neuromorphic applications. However, the implementation of such a functionality in conventional CMOS design requires expensive hardware and involves significant power consumption. Even power-efficient current-mode analog designs have proved to be slower and vulnerable to variations. In this paper, we propose an approximate mixed-signal design for the distance computing core by noting the fact that a vast majority of the signal processing applications involving this operation are resilient to small approximations in the distance computation. The proposed mixed-signal design is able to interface with external digital CMOS logic and simultaneously exhibit fast operating speeds. Another important feature of the proposed design is that the computing core is able to compute two variants of the distance metric, namely the (i) Euclidean distance squared (L22 norm) and (ii) Manhattan distance (L1 norm). The performance of the proposed design was evaluated on a standard K-means clustering algorithm on the “Iris flower dataset”. The results indicate a throughput of 6 ns per classification and ∼2.3× lower energy consumption in comparison to a synthesized digital CMOS design in commercial 45 nm CMOS technology.

Components of Artificial Neural Networks Realized in CMOS Technology to be Used in Intelligent Sensors in Wireless Sensor Networks

The article presents novel hardware solutions for new intelligent sensors that can be used in wireless sensor networks (WSN). A substantial reduction of the amount of data sent by the sensor to the base station in the WSN may extend the possible sensor working time. Miniature integrated artificial neural networks (ANN) applied directly in the sensor can take over the analysis of data collected from the environment, thus reducing amount of data sent over the RF communication block. A prototype specialized chip with components of the ANN was designed in the CMOS 130 nm technology. An adaptation mechanism and a programmable multi-phase clock generator—components of the ANN—are described in more detail. Both simulation and measurement results of selected blocks are presented to demonstrate the correctness of the design.