Implications of interconnection theory for optical digital computing

Toward an optimal foundation architecture for optoelectronic computing. Part I. Regularly interconnected device planes

By systematically examining the tree of possibilities for optoelectronic computing architectures and offering arguments that allow one to prune suboptimal branches of this tree, I come to the conclusion that electronic circuit planes interconnected optically according to regular connection patterns represent an alternative that is reasonably close to the best possible, as defined by physical limitations. Thus I propose that this foundation architecture should provide a basis for future research and development in this area.

Impact of gate fan-in and fan-out limits on optoelectronic digital circuits

The impact of gate fan-in and fan-out limits on digital circuit delay is discussed with a set of benchmark circuits. This research presents the advantages of exploiting the ability of optoelectronic gates to perform both logic operations and optical interconnections with systematic optimization. It is possible for gate-level optical interconnected optoelectronic circuits to compete with their pure silicon counterparts in terms of the combinational circuit delay and system clock rate.

Elements of a hybrid interconnection theory

We present a textbooklike treatment of hybrid systems employing both optical and electrical interconnections. We investigate how these two different interconnection media can be used in conjunction to realize a system not possible with any alone. More specifically, we determine the optimal mix of optical and normally conducting interconnections maximizing a given figure-of-merit function. We find that optical interconnections have relatively little to offer if the optical paths are constrained to lie on a plane (such as in an integrated optics system). However, if optical paths are permitted to leave the plane, they may enable considerable increase in performance. In any event the prize in terms of performance is accompanied by a penalty in terms of system power and/or size.