Toward a free-space parallel optoelectronic computer: a 300-MHz optoelectronic counter using holographic interconnects

Simulating free-space optical computing architectures

Major issues in optoelectronic system design include timing, synchronization, and control. Designing free-space optical computing architectures is difficult because of the high degree of system complexity, parallelism, and concurrency in conjunction with the high cost and lack of availability of devices. Current simulation tools lack the expressiveness to model the system structure and behavior of parallel and concurrent architectures, thus making them inefficient and ineffective. We show that Petri nets, compared with other system-modeling methodologies, are more efficient and effective at expressing the functional, behavioral, and structural properties of parallel and concurrent architectures. We show how an extended version of the standard Petri net, a timed-colored Petri net, is used to model and simulate free-space optoelectronic computing architectures. We also present methods for analysis of system timing, synchronization, and control behavior.

Impact of gate fan-in and fan-out limits on optoelectronic digital circuits

The impact of gate fan-in and fan-out limits on digital circuit delay is discussed with a set of benchmark circuits. This research presents the advantages of exploiting the ability of optoelectronic gates to perform both logic operations and optical interconnections with systematic optimization. It is possible for gate-level optical interconnected optoelectronic circuits to compete with their pure silicon counterparts in terms of the combinational circuit delay and system clock rate.