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For: Navarro-Torres A, Alastruey-Benedé J, Ibáñez-Marín P, Viñals-Yúfera V. Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP. PLoS One 2019;14:e0220135. [PMID: 31369592 PMCID: PMC6675054 DOI: 10.1371/journal.pone.0220135] [Citation(s) in RCA: 6] [Impact Index Per Article: 1.2] [Reference Citation Analysis] [What about the content of this article? (0)] [Track Full Text] [Download PDF] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 01/24/2019] [Accepted: 07/09/2019] [Indexed: 11/18/2022]  Open
Number Cited by Other Article(s)
1
Navarro-Torres A, Alastruey-Benedé J, Ibáñez-Marín P, Viñals-Yúfera V. Correction: Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP. PLoS One 2024;19:e0303712. [PMID: 38722938 PMCID: PMC11081277 DOI: 10.1371/journal.pone.0303712] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Journal Information] [Subscribe] [Scholar Register] [Indexed: 05/13/2024]  Open
2
Escuin C, Ibáñez P, Navarro D, Monreal T, Llabería JM, Viñals V. L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime. PLoS One 2023;18:e0278346. [PMID: 36749765 PMCID: PMC9904472 DOI: 10.1371/journal.pone.0278346] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [MESH Headings] [Grants] [Track Full Text] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 06/10/2022] [Accepted: 11/10/2022] [Indexed: 02/08/2023]  Open
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