Automatic Calibration Method of Channel Mismatches for Wideband TI-ADC System

Pulse Compression Shape-Based ADC/DAC Chain Synchronization Measurement Algorithm with Sub-Sampling Resolution

In this article, we address the problem of synchronizing multiple analog-to-digital converter (ADC) and digital-to-analog converter (DAC) chains in a multi-channel system, which is constrained by the sampling frequency and inconsistencies among the components during system integration. To evaluate and compensate for the synchronization differences, we propose a pulse compression shape-based algorithm to measure the entire delay parameter of the ADC/DAC chain, which achieves sub-sampling resolution by mapping the shape of the discrete pulse compression peak to the signal propagation delay. Moreover, owing to the matched filtering in the pulse compression process, the algorithm exhibits good noise performance and is suitable for wireless scenarios. Experiments verified that the algorithm can achieve precise measurements with sub-sampling resolution in scenarios where the signal-to-noise ratio (SNR) is greater than -10 dB.

Time-interleaved system mismatch estimation based on correlation function and particle swarm optimization algorithm

The time-interleaved analog-to-digital converters (TIADCs) technique is an efficient solution to improve the sampling rate of the acquisition system with low-speed ADCs. However, channel mismatches such as gain mismatch, time skew mismatch, and offset mismatch may seriously degrade the performance of TIADC. Furthermore, for high-speed signal acquisition, the gain and time skew mismatches would vary with the signal frequency, and the traditional fixed model does not work any longer. In this paper, a series of sinusoidal signals are adopted to estimate the variable mismatches. First, an autocorrelation-based approach is presented to estimate the gain mismatch. The information about the gain mismatch is extracted from the autocorrelation function of sub-ADC output samples. Then, the time skew mismatch is estimated by utilizing the particle swarm optimization algorithm. The reported simulation results show that the mismatches can be accurately estimated. Finally, a commercial 12.5 GSPS four-channel TIADC system is utilized to verify the performance of the proposed method. The spurious free dynamic range of the system can be improved by about 20 dB, and the effectiveness of the proposed estimation method is demonstrated.

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

The performance of analog-to-digital converters (ADCs) has reached a bottleneck due to the limitations of the manufacturing process and testing environment. Time-interleaved ADC (TIADC) technology can increase the sampling rate without changing the resolution. However, channel mismatch severely degrades the dynamic performance of the TIADC system. For the channel mismatch problem of TIADC, most of the current solutions have preconditions, such as eliminating only some kind of error or increasing the complexity of the hardware. A few methods can estimate multiple errors without changing the hardware circuit. To improve the dynamic performance of the TIADC system, on the basis of an in-depth study of the channel mismatch error of TIADC, according to the system identification theory, an identification model is designed to characterize the frequency characteristics of TIADC. Using the system observation data, the transfer function parameters of the system are recursively estimated. By constructing and verifying the identification model of the TIADC system, and then through the frequency domain correction method, a digital compensation filter is established to complete the error correction of the system. The test results of the four-channel TIADC high-speed data acquisition system show that the actual input and output characteristics of the test system are consistent with the nature of the identification model. The four channels of the TIADC system are provided by four sub-channels of two AD9653 chips, and the highest sampling rate of a single channel is 125MSPS. For sinusoidal input signals from 20 MHz to 150 MHz, the sampling system can achieve a signal-to-noise ratio (SNR) above 56.8 dB and spurious free dynamic range (SFDR) above 69.7 dB. The dynamic performance of the sampling system is nearly equivalent to that of its sub-ADC; the feasibility of the model identification method and the effectiveness of error correction are verified in simulation and experiment.

Enabling Fine Sample Rate Settings in DSOs with Time-Interleaved ADCs

The time-base used by digital storage oscilloscopes allows limited selections of the sample rate, namely constrained to a few integer submultiples of the maximum sample rate. This limitation offers the advantage of simplifying the data transfer from the analog-to-digital converter to the acquisition memory, and of assuring stability performances, expressed in terms of absolute jitter, that are independent of the chosen sample rate. On the counterpart, it prevents an optimal usage of the memory resources of the oscilloscope and compels to post processing operations in several applications. A time-base that allows selecting the sample rate with very fine frequency resolution, in particular as a rational submultiple of the maximum rate, is proposed. The proposal addresses the oscilloscopes with time-interleaved converters, that require a dedicated and multifaceted approach with respect to architectures where a single monolithic converter is in charge of signal digitization. The proposed time-base allows selecting with fine frequency resolution sample rate values up to 200 GHz and beyond, still assuring jitter performances independent of the sample rate selection.

Frequency response mismatch calibration in 2-channel time-interleaved oscilloscopes

The time-interleaved (TI) structure has been widely implemented in high speed, wideband data acquisition systems to increase the system sampling rate. However, the frequency responses of each sub-sampling path are not identical. This is named frequency response mismatches (FRMs). In TI-based printed circuit board level systems, due to the impact of the parasitic parameters, the FRMs are more complicated than the mismatches in TI analog-to-digital converters (TIADCs), which degrade the system performance severely. Therefore, the FRM calibration in 2-channel TI acquisition systems with two features is researched. The first one is that the TI system has a larger mismatch range than in most previous research. The second one is that the channel frequency response uses the general model. The calibration structure is established by the analysis of the digital TI model, which implements the TI operation in the digital domain to reconstruct the mismatches in the time domain. Furthermore, the problem of designing an arbitrary frequency response filter is transformed to the question of designing a three-stage cascaded filter group, which gives a method to realize the arbitrary frequency response in a real system. An oscilloscope prototype is proposed to verify the calibration performance. The simulation and experiment show the following: (i) Even though it uses the general frequency response and the FRMs are significant, the proposed method is still effective. (ii) The mismatch range of magnitude and phase responses is highly suppressed, and the spurious-free dynamic range is improved by 16.26 dB after calibration of the prototype.

Categorization and Characterization of Time Domain CMOS Temperature Sensors

Time domain complementary metal-oxide-semiconductor (CMOS) temperature sensors estimate the temperature of a sensory device by measuring the frequency, period and/or delay time instead of the voltage and/or current signals that have been traditionally measured for a long time. In this paper, the time domain CMOS temperature sensors are categorized into twelve types by using the temperature estimation function which is newly defined as the ratio of two measured time domain signals. The categorized time domain CMOS temperature sensors, which have been published in literature, show different characteristics respectively in terms of temperature conversion rate, die area, process variation compensation, temperature error, power supply voltage sensitivity and so on. Based on their characteristics, we can choose the most appropriate one from twelve types to satisfy a given specification.

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.