Theoretical and Experimental Investigation of Warpage Evolution of Flip Chip Package on Packaging during Fabrication

Development of ANN-Based Warpage Prediction Model for FCCSP via Subdomain Sampling and Taguchi Hyperparameter Optimization

This study aims to establish an accurate prediction model using artificial neural networks (ANNs) to effectively and efficiently predict the process-induced warpage of a flip-chip chip-scale package (FCCSP). To enhance model performance, a novel subdomain-based sampling strategy and Taguchi hyperparameter optimization are proposed in the ANN algorithm. To simulate the warpage behavior the FCCSP during fabrication, a process modeling approach is proposed, where the viscoelastic behavior of the epoxy molding compound is included, in which the viscoelastic properties are determined using dynamic mechanical measurement. In addition, the temperature-dependent thermal-mechanical properties of the materials in the FCCSP are assessed through thermal-mechanical analysis and dynamic mechanical analysis. The modeled warpage results are verified by the warpage measurement. Next, warpage parametric analysis is performed to identify the key factors most affecting warpage behavior for use in the construction of the warpage prediction model. Moreover, the advantages of the proposed sampling and hyperparameter tuning approaches are proved by comparing with other existing models, and the validity of the developed ANN-based deep learning warpage prediction model is demonstrated through a validation dataset.

Investigation of Warpage for Multi-Die Fan-Out Wafer-Level Packaging Process

This paper focuses on characterizing the evolution of warpage, effects of epoxy molding compound (EMC), and effects of carrier 2 (the second carrier in the process) of 12 inch RDL-first multi-die fan-out wafer-level packaging (FOWLP) during the manufacturing process. The linear viscoelasticity properties of EMC and polyimide (PI) were characterized using dynamic mechanical analysis (DMA) in the frequency domain at different temperatures., The elastic and viscoelastic model were used for PI and EMC, the finite element analyses (FEA) of the cured structure were carried out and the results were compared with the test results. The viscoelastic properties of the EMC in the FEA could predict the wafer warpage more accurately. The FEA and experiments were used to investigate the evolution of warpage. The molding had a great influence on the warpage. The effects of the EMC and carrier 2 were also investigated with FEA. The wafer warpage could be reduced by lowering the thickness of the EMC, increasing the thickness of carrier 2, and selecting EMC and carrier 2 with a matched coefficient of thermal expansion (CTE).

Study on the Strip Warpage Issues Encountered in the Flip-Chip Process

This study successfully established a strip warpage simulation model of the flip-chip process and investigated the effects of structural design and process (molding, post-mold curing, pretreatment, and ball mounting) on strip warpage. The errors between simulated and experimental values were found to be less than 8%. Taguchi analysis was employed to identify the key factors affecting strip warpage, which were discovered to be die thickness and substrate thickness, followed by mold compound thickness and molding temperature. Although a greater die thickness and mold compound thickness reduce the strip warpage, they also substantially increase the overall strip thickness. To overcome this problem, design criteria are proposed, with the neutral axis of the strip structure located on the bump. The results obtained using the criteria revealed that the strip warpage and overall strip thickness are effectively reduced. In summary, the proposed model can be used to evaluate the effect of structural design and process parameters on strip warpage and can provide strip design guidelines for reducing the amount of strip warpage and meeting the requirements for light, thin, and short chips on the production line. In addition, the proposed guidelines can accelerate the product development cycle and improve product quality with reduced development costs.