A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core-Insulator

Leakage and Thermal Reliability Optimization of Stacked Nanosheet Field-Effect Transistors with SiC Layers

In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the gate, with SiC layers under the source and drain, to improve the leakage current and thermal reliability. Punch-through stopper (PTS) doping is widely used to suppress the leakage current, but aggressively high PTS doping will cause additional band-to-band (BTBT) current. Therefore, the bottom oxide isolation nanosheet field-effect transistor (BOX-NSFET) can further reduce the leakage current and become an alternative to conventional structures with PTS. However, thermal reliability issues, like bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB), induced by the self-heating effect (SHE) of BOX-NSFET, become more profound due to the lower thermal conductivity of SiO2 than silicon. Moreover, the bottom oxide will reduce the stress along the channel due to the challenges associated with growing high-quality SiGe material on SiO2. Therefore, this method faces difficulties in enhancing the mobility of p-type devices. The comprehensive TCAD simulation results show that SiC-NSFET significantly suppresses the substrate leakage current compared to the conventional structure with PTS. In addition, compared to the BOX-NSFET, the stress reduction caused by the bottom oxide is avoided, and the SHE is mitigated. This work provides significant design guidelines for leakage and thermal reliability optimization of next-generation advanced nodes.

A New Approach to Modeling Ultrashort Channel Ballistic Nanowire GAA MOSFETs

We propose a numerical compact model for describing the drain current in ballistic mode by using an expression to represent the transmission coefficients for all operating regions. This model is based on our previous study of an analytic compact model for the subthreshold region in which the DIBL and source-to-drain tunneling effects were both taken into account. This paper introduces an approach to establishing the smoothing function for expressing the critical parameters in the model's overall operating regions. The resulting compact model was tested in a TCAD NEGF simulation, demonstrating good consistency.

Gate-all-around junctionless FET based label-free dielectric/charge modulation detection of SARS-CoV-2 virus

The recent corona outbreak has necessitated the development of a label-free, highly sensitive, fast, accurate, and cost-effective biosensor for the detection of SARS-CoV-2 virus. This study records the label-free electrical detection of the SARS-CoV-2 virus using the gate-all-around junctionless field effect transistor (GAA-JLFET) that detects the virus because of the electrical properties (dielectric constant and charge) of spike protein, envelope protein, and virus DNA, for a highly sensitive and real-time bio-sensor. GAA-JLFETs are suitable for this application because of their highest gate controllability, potential vertical stacking, current industry trend compatibility, inherent ease of fabrication, and higher sensitivity. The SARS-CoV-2 virus is first immobilized in the etched nano-cavity embedded beneath the gate electrode, which is then used to detect it. The SARS-CoV-2 virus detection has been calibrated based on the change in system electrical properties after virus immobilization. For effective virus detection, the work takes into account both the dielectric property of S protein and the charge of DNA at the same time. The sensitivity has been calculated using ΔV _TH, ΔI _ON, Δg _m, and ΔSS. The simulation analysis also shows a simpler recovery mechanism in this case.