A High Performance Delta-Sigma Modulator for Neurosensing

A bioelectric neural interface towards intuitive prosthetic control for amputees

OBJECTIVE

While prosthetic hands with independently actuated digits have become commercially available, state-of-the-art human-machine interfaces (HMI) only permit control over a limited set of grasp patterns, which does not enable amputees to experience sufficient improvement in their daily activities to make an active prosthesis useful.

APPROACH

Here we present a technology platform combining fully-integrated bioelectronics, implantable intrafascicular microelectrodes and deep learning-based artificial intelligence (AI) to facilitate this missing bridge by tapping into the intricate motor control signals of peripheral nerves. The bioelectric neural interface includes an ultra-low-noise neural recording system to sense electroneurography (ENG) signals from microelectrode arrays implanted in the residual nerves, and AI models employing the recurrent neural network (RNN) architecture to decode the subject's motor intention.

MAIN RESULTS

A pilot human study has been carried out on a transradial amputee. We demonstrate that the information channel established by the proposed neural interface is sufficient to provide high accuracy control of a prosthetic hand up to 15 degrees of freedom (DOF). The interface is intuitive as it directly maps complex prosthesis movements to the patient's true intention.

SIGNIFICANCE

Our study layouts the foundation towards not only a robust and dexterous control strategy for modern neuroprostheses at a near-natural level approaching that of the able hand, but also an intuitive conduit for connecting human minds and machines through the peripheral neural pathways. (Clinical trial identifier: NCT02994160).

Noise Optimization Techniques for Switched-Capacitor Based Neural Interfaces

This paper presents the noise optimization of a novel switched-capacitor (SC) based neural interface architecture, and its circuit demonstration in a 0.13 [Formula: see text] CMOS process. To reduce thermal noise folding ratio, and suppress kT/C noise, several noise optimization techniques are developed in the proposed architecture. First, one parasitic capacitance suppression scheme is developed to block noise charge transfer from parasitic capacitors to amplifier output. Second, one recording path-splitting scheme is proposed in the input sampling stage to selectively record local field potentials (LFPs), extracellular spikes, or both for reducing input noise floor, and total power consumption. Third, an auto-zero noise cancellation scheme is developed to suppress kT/C noise in the neural amplifier stage. A prototype neural interface chip was fabricated, and also verified in both bench-top, and In-Vivo experiments. Bench-top testings show the input-referred noise of the designed chip is 4.8 [Formula: see text] from 1 [Formula: see text] to 300 [Formula: see text], and 2.3 [Formula: see text] from 300 [Formula: see text] to 8 kHz respectively, and In-Vivo experiments show the peak-to-peak amplitude of the total noise floor including neural activity, electrode interface noise, and the designed chip is only around 20 [Formula: see text]. In comparison with conventional architectures through both circuit measurement and animal experiments, it is well demonstrated that the proposed noise optimization techniques can effectively reduce circuit noise floor, thus extending the application range of switched-capacitor circuits.

A Wide Dynamic Range Neural Data Acquisition System With High-Precision Delta-Sigma ADC and On-Chip EC-PC Spike Processor

A high-performance, wide dynamic range, fully-integrated neural interface is one key component for many advanced bidirectional neuromodulation technologies. In this paper, to complement the previously proposed frequency-shaping amplifier (FSA) and high-precision electrical microstimulator, we will present a proof-of-concept design of a neural data acquisition (DAQ) system that includes a 15-bit, low-power Delta-Sigma analog-to-digital converter (ADC) and a real-time spike processor based on one exponential component-polynomial component (EC-PC) algorithm. High-precision data conversion with low power consumption and small chip area is achieved by employing several techniques, such as opamp-sharing, multi-bit successive approximation (SAR) quantizer, two-step summation, and ultra-low distortion data weighted averaging (DWA). The on-chip EC-PC engine enables low latency, automatic detection, and extraction of spiking activities, thus supporting closed-loop control, real-time data compression and /or neural information decoding. The prototype chip was fabricated in a 0.13  μm CMOS process and verified in both bench-top and In-Vivo experiments. Bench-top measurement results indicate the designed ADC achieves a peak signal-to-noise and distortion ratio (SNDR) of 91.8 dB and a dynamic range of 93.0 dB over a 10 kHz bandwidth, where the total power consumption of the modulator is only 20  μW at 1.0 V supply, corresponding to a figure-of-merit (FOM) of 31.4fJ /conversion-step. In In-Vivo experiments, the proposed DAQ system has been demonstrated to obtain high-quality neural activities from a rat's motor cortex and also greatly reduce recovery time from system saturation due to electrical microstimulation.

A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

This paper describes a fourth-order cascade-of-integrators with feedforward (CIFF) single-bit discrete-time (DT) switched-capacitor (SC) delta-sigma modulator (DSM) for high-resolution applications. This DSM is suitable for high-resolution applications at low frequency using a high-order modulator structure. The proposed operational transconductance amplifier (OTA), used a feedforward amplifier scheme that provided a high-power efficiency, a wider bandwidth, and a higher DC gain compared to recent designs. A chopper-stabilization technique was applied to the first integrator to remove the 1/f noise from the transistor, which is inversely proportional to the frequency. The designed DSM was implemented using 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The oversampling ratio (OSR) was 128, and the sampling frequency was 128 kHz. At a 500 Hz bandwidth, the signal-to-noise ratio (SNR) was 100.3 dB, the signal-to-noise distortion ratio (SNDR) was 98.5 dB, and the dynamic range (DR) was 103 dB. The measured total power dissipation was 99 µW from a 3.3 V supply voltage.