A CMOS Low Pass Filter for SoC Lock-in-Based Measurement Devices

Analog Lock-In Amplifier Design Using Subsampling for Accuracy Enhancement in GMI Sensor Applications

A frequency downscaling technique for enhancing the accuracy of analog lock-in amplifier (LIA) architectures in giant magneto-impedance (GMI) sensor applications is presented in this paper. As a proof of concept, the proposed method is applied to two different LIA topologies using, respectively, analog and switching-based multiplication for phase-sensitive detection. Specifically, the operation frequency of both the input and the reference signals of the phase-sensitive detector (PSD) block of the LIA is reduced through a subsampling process using sample-and-hold (SH) circuits. A frequency downscaling from 200 kHz, which is the optimal operating frequency of the employed GMI sensor, to 1 kHz has been performed. In this way, the proposed technique exploits the inherent advantages of analog signal multiplication at low frequencies, while the principle of operation of the PSD remains unaltered. The circuits were assembled using discrete components, and the frequency downscaling proposal was experimentally validated by comparing the measurement accuracy with the equivalent conventional circuits. The experimental results revealed that the error in the signal magnitude measurements was reduced by a factor of 8 in the case of the analog multipliers and by a factor of 21 when a PSD based on switched multipliers was used. The error in-phase detection using a two-phase LIA was also reduced by more than 25%.

A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a −40 to 120 °C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.

1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-V_pp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-V_pp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

Gradient Estimator-Based Amplitude Estimation for Dynamic Mode Atomic Force Microscopy: Small-Signal Modeling and Tuning

Atomic force microscopy (AFM) plays an important role in nanoscale imaging application. AFM works by oscillating a microcantilever on the surface of the sample being scanned. In this process, estimating the amplitude of the cantilever deflection signal plays an important role in characterizing the topography of the surface. Existing approaches on this topic either have slow dynamic response e.g., lock-in-amplifier or high computational complexity e.g., Kalman filter. In this context, gradient estimator can be considered as a trade-off between fast dynamic response and high computational complexity. However, no constructive tuning rule is available in the literature for gradient estimator. In this paper, we consider small-signal modeling and tuning of gradient estimator. The proposed approach greatly simplifies the tuning procedure. Numerical simulation and experimental results are provided to demonstrate the suitability of the proposed tuning procedure.