A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces

A Low-Voltage Low-Power Voltage-to-Current Converter with Low Temperature Coefficient Design Awareness

This paper presents a low-voltage, low-power voltage-to-current converter (V-I Converter) implemented in TSMC 40 nm CMOS technology. Operating at a supply voltage of 0.45 V with an input range of 0.1 V to 0.3 V, the proposed circuit achieves a temperature coefficient of 54.68 ppm/°C, which is at least 2× better than prior works, ensuring stable performance across a wide temperature range (-20 °C to 80 °C). The design employs a three-stage operational transconductance amplifier (OTA) with a Q-reduction frequency compensation technique to produce programmable output currents while maintaining a power dissipation of less than 2.76 μW. With a bandwidth of 34.45 kHz and a total harmonic distortion (THD) of -56.66 dB at 1 kHz and 0.1 VPP input signal, the circuit demonstrates high linearity and low power consumption under ultra-low voltage design scenarios. These features make the proposed V-I Converter highly suitable for energy-constrained applications such as biomedical sensors, energy harvesting systems, and IoT nodes, where low power consumption and temperature stability are critical parameters.

Ladder-Based Synthesis and Design of Low-Frequency Buffer-Based CMOS Filters

Buffer-based CMOS filters are maximally simplified circuits containing as few transistors as possible. Their applications, among others, include nano to micro watt biomedical sensors that process physiological signals of frequencies from 0.01 Hz to about 3 kHz. The order of a buffer-based filter is not greater than two. Hence, to obtain higher-order filters, a cascade of second-order filters is constructed. In this paper, a more general method for buffer-based filter synthesis is developed and presented. The method uses RLC ladder prototypes to obtain filters of arbitrary orders. In addition, a set of novel circuit solutions with ultra-low voltage and power are proposed. The introduced circuits were synthesized and simulated using 180-nm CMOS technology of X-FAB. One of the designed circuits is a fourth-order, low-pass filter that features: 100-Hz passband, 0.4-V supply voltage, power consumption of less than 5 nW, and dynamic range above 60 dB. Moreover, the total capacitance of the proposed filter (31 pF) is 25% lower compared to the structure synthesized using a conventional cascade method (40 pF).

A 1.9 nW, Sub-1 V, 542 pA/V Linear Bulk-Driven OTA with 154 dB CMRR for Bio-Sensing Applications

In this paper, a new technique for improvement on the DC voltage gain, while keeping the high-linearity in symmetrical operational transconductance amplifier (OTA) bulk-driven (BD) topology is proposed. These features are achieved by allying two topological solutions: enhanced forward-body-biasing self-cascode current mirror, and source degeneration. The proposed concept is demonstrated through simulations with typical process parameters and Monte Carlo analysis on nominal transistors of the CMOS TSMC 180 nm node. Results indicate that the proposed OTA can achieve a very small transconductance, only 542 pA/V while keeping a voltage gain higher than 60 dB, 150 dB CMRR, and high linearity of 475 mVpp (1% THD), consuming only 1.9 nW for a supply voltage of 0.6 V. This set of features allows the proposed OTA to be an attractive solution for implementing OTA-C filters for the analog front-ends in wearable devices and bio-sensing.

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

In this paper, a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs), using the gm/ID approach, is proposed for the Internet-of-things (IoT) scenario. The strategy optimizes the speed/dissipation of the OTA in terms of settling time, including slew-rate effects. It was designed for large capacitive loads and for transistors biased in the sub-threshold region, but it is also suitable for low-capacitive loads or for transistors biased in the saturation region. To validate the proposed strategy, a well-known three-stage OTA was designed starting from capacitive load and settling time requirements. Simulations confirmed that the OTA satisfies the specifications (even under Monte Carlo analysis), thus proving the correctness of the proposed approach.