Memristor-based cellular nonlinear/neural network: design, analysis, and applications

Cellular nonlinear/neural network (CNN) has been recognized as a powerful massively parallel architecture capable of solving complex engineering problems by performing trillions of analog operations per second. The memristor was theoretically predicted in the late seventies, but it garnered nascent research interest due to the recent much-acclaimed discovery of nanocrossbar memories by engineers at the Hewlett-Packard Laboratory. The memristor is expected to be co-integrated with nanoscale CMOS technology to revolutionize conventional von Neumann as well as neuromorphic computing. In this paper, a compact CNN model based on memristors is presented along with its performance analysis and applications. In the new CNN design, the memristor bridge circuit acts as the synaptic circuit element and substitutes the complex multiplication circuit used in traditional CNN architectures. In addition, the negative differential resistance and nonlinear current-voltage characteristics of the memristor have been leveraged to replace the linear resistor in conventional CNNs. The proposed CNN design has several merits, for example, high density, nonvolatility, and programmability of synaptic weights. The proposed memristor-based CNN design operations for implementing several image processing functions are illustrated through simulation and contrasted with conventional CNNs. Monte-Carlo simulation has been used to demonstrate the behavior of the proposed CNN due to the variations in memristor synaptic weights.

A novel method based on two cameras for accurate estimation of arterial oxygen saturation

BACKGROUND

Photoplethysmographic imaging (PPGi) that is based on camera allows acquiring photoplethysmogram and measuring physiological parameters such as pulse rate, respiration rate and perfusion level. It has also shown potential for estimation of arterial oxygen saturation (SaO2). However, there are some technical limitations such as optical shunting, different camera sensitivity to different light spectra, different AC-to-DC ratios (the peak-to-peak amplitude to baseline ratio) of the PPGi signal for different portions of the sensor surface area, the low sampling rate and the inconsistency of contact force between the fingertip and camera lens.

METHODS

In this paper, we take full account of the above-mentioned design challenges and present an accurate SaO2 estimation method based on two cameras. The hardware system we used consisted of an FPGA development board (XC6SLX150T-3FGG676 from Xilinx), with connected to it two commercial cameras and an SD card. The two cameras were placed back to back, one camera acquired PPGi signal from the right index fingertip under 660 nm light illumination while the other camera acquired PPGi signal from the thumb fingertip using an 800 nm light illumination. The both PPGi signals were captured simultaneously, recorded in a text file on the SD card and processed offline using MATLAB®. The calculation of SaO2 was based on the principle of pulse oximetry. The AC-to-DC ratio was acquired by the ratio of powers of AC and DC components of the PPGi signal in the time-frequency domain using the smoothed pseudo Wigner-Ville distribution. The calibration curve required for SaO2 measurement was obtained by linear regression analysis.

RESULTS

The results of our estimation method from 12 subjects showed a high correlation and accuracy with those of conventional pulse oximetry for the range from 90 to 100%.

CONCLUSIONS

Our method is suitable for mobile applications implemented in smartphones, which could allow SaO2 measurement in a pervasive environment.

Experimental demonstration of a second-order memristor and its ability to biorealistically implement synaptic plasticity

Memristors have been extensively studied for data storage and low-power computation applications. In this study, we show that memristors offer more than simple resistance change. Specifically, the dynamic evolutions of internal state variables allow an oxide-based memristor to exhibit Ca(2+)-like dynamics that natively encode timing information and regulate synaptic weights. Such a device can be modeled as a second-order memristor and allow the implementation of critical synaptic functions realistically using simple spike forms based solely on spike activity.

Memristor crossbar-based neuromorphic computing system: a case study

By mimicking the highly parallel biological systems, neuromorphic hardware provides the capability of information processing within a compact and energy-efficient platform. However, traditional Von Neumann architecture and the limited signal connections have severely constrained the scalability and performance of such hardware implementations. Recently, many research efforts have been investigated in utilizing the latest discovered memristors in neuromorphic systems due to the similarity of memristors to biological synapses. In this paper, we explore the potential of a memristor crossbar array that functions as an autoassociative memory and apply it to brain-state-in-a-box (BSB) neural networks. Especially, the recall and training functions of a multianswer character recognition process based on the BSB model are studied. The robustness of the BSB circuit is analyzed and evaluated based on extensive Monte Carlo simulations, considering input defects, process variations, and electrical fluctuations. The results show that the hardware-based training scheme proposed in the paper can alleviate and even cancel out the majority of the noise issue.

A lightweight distributed framework for computational offloading in mobile cloud computing

The latest developments in mobile computing technology have enabled intensive applications on the modern Smartphones. However, such applications are still constrained by limitations in processing potentials, storage capacity and battery lifetime of the Smart Mobile Devices (SMDs). Therefore, Mobile Cloud Computing (MCC) leverages the application processing services of computational clouds for mitigating resources limitations in SMDs. Currently, a number of computational offloading frameworks are proposed for MCC wherein the intensive components of the application are outsourced to computational clouds. Nevertheless, such frameworks focus on runtime partitioning of the application for computational offloading, which is time consuming and resources intensive. The resource constraint nature of SMDs require lightweight procedures for leveraging computational clouds. Therefore, this paper presents a lightweight framework which focuses on minimizing additional resources utilization in computational offloading for MCC. The framework employs features of centralized monitoring, high availability and on demand access services of computational clouds for computational offloading. As a result, the turnaround time and execution cost of the application are reduced. The framework is evaluated by testing prototype application in the real MCC environment. The lightweight nature of the proposed framework is validated by employing computational offloading for the proposed framework and the latest existing frameworks. Analysis shows that by employing the proposed framework for computational offloading, the size of data transmission is reduced by 91%, energy consumption cost is minimized by 81% and turnaround time of the application is decreased by 83.5% as compared to the existing offloading frameworks. Hence, the proposed framework minimizes additional resources utilization and therefore offers lightweight solution for computational offloading in MCC.

MDGRAPE-4: a special-purpose computer system for molecular dynamics simulations

We are developing the MDGRAPE-4, a special-purpose computer system for molecular dynamics (MD) simulations. MDGRAPE-4 is designed to achieve strong scalability for protein MD simulations through the integration of general-purpose cores, dedicated pipelines, memory banks and network interfaces (NIFs) to create a system on chip (SoC). Each SoC has 64 dedicated pipelines that are used for non-bonded force calculations and run at 0.8 GHz. Additionally, it has 65 Tensilica Xtensa LX cores with single-precision floating-point units that are used for other calculations and run at 0.6 GHz. At peak performance levels, each SoC can evaluate 51.2 G interactions per second. It also has 1.8 MB of embedded shared memory banks and six network units with a peak bandwidth of 7.2 GB s(-1) for the three-dimensional torus network. The system consists of 512 (8×8×8) SoCs in total, which are mounted on 64 node modules with eight SoCs. The optical transmitters/receivers are used for internode communication. The expected maximum power consumption is 50 kW. While MDGRAPE-4 software has still been improved, we plan to run MD simulations on MDGRAPE-4 in 2014. The MDGRAPE-4 system will enable long-time molecular dynamics simulations of small systems. It is also useful for multiscale molecular simulations where the particle simulation parts often become bottlenecks.

Disordered self assembled monolayer dielectric induced hysteresis in organic field effect transistors

A memory device using an organic field effect transistor (OFET) with copper phthalocyanine (CuPc) as active material was fabricated and studied. For this purpose, SiO2 dielectric surface was modified with a disordered self assembled monolayer (SAM) of octadecyltrichlorosilane (OTS) molecule which was found to induce large disorder in CuPc film thereby generating more traps for charge carriers. Drain current-drain voltage characteristics at zero gate voltage exhibited large hysteresis which was not observed in OFET devices with ordered OTS monolayer modified and unmodified SiO2 dielectrics. The extent of hysteresis and drain current on/off ratio, reading voltage etc. were found to be dependent on the sweep rate/step voltage employed during scanning. Highest hysteresis with on/off ratio of about 240 was obtained for an optimum step voltage of 2 V while it decreased with further reduction in the same. This was attributed to the longer scanning time leading to release of trapped carriers during forward scan itself. The OFET device was found to exhibit excellent memory retention capability where OFF and ON current measured for about 2 hours after stressing the device at write and erase voltages showed good retention of on/off ratio.

Temperature dependence of resistive switching behaviors in resistive random access memory based on graphene oxide film

We reported resistive switching behaviors in the resistive random access memory (RRAM) devices based on the different annealing temperatures of graphene oxide (GO) film as active layers. It was found that the resistive switching characteristics of an indium tin oxide (ITO)/GO/Ag structure have a strong dependence on the annealing temperature of GO film. When the annealing temperature of the GO film was 20 °C, the devices showed typical write-once-read-many-times (WORM) type memory behaviors, which have good memory performance with a higher ON/OFF current ratio (∼10(4)), the higher the high resistance state (HRS)/low resistance state (LRS) ratio (∼10(5)) and stable retention characteristics (>10(3) s) under lower programming voltage (-1 V and -0.5 V). With the increasing annealing temperature of GO film, the resistive switching behavior of RRAM devices gradually weakened and eventually disappeared. This phenomenon could be understood by the different energy level distributions of the charge traps in GO film, and the different charge injection ability from the Ag electrode to GO film, which is caused by the different annealing temperatures of the GO film.

A new bipolar RRAM selector based on anti-parallel connected diodes for crossbar applications

Crossbar arrays are the most promising application of a resistive random access memory (RRAM) device for achieving high density memory. However, cross-talk interference in the crossbar array limits the increase in the integration density. In this paper, the combination of two anti-parallel connected diodes and a bipolar RRAM cell is proposed to suppress the sneak current in a crossbar array with anti-parallel connected diodes as the selector for the bipolar RRAM. By using the anti-parallel connected diodes as a selector, the sneak current can be effectively suppressed and the high density crossbar array of more than 1 Mb can be realized as estimated by the 1/2V read voltage scheme. These results indicate that anti-parallel connected diodes can be used as a bipolar selector and have great potential for high density bipolar RRAM crossbar array applications.

The impact of tunnel oxide nitridation to reliability performance of charge storage non-volatile memory devices

This paper is written to review the development of critical research on the overall impact of tunnel oxide nitridation (TON) with the aim to mitigate reliability issues due to incessant technology scaling of charge storage NVM devices. For more than 30 years, charge storage non-volatile memory (NVM) has been critical in the evolution of intelligent electronic devices and continuous development of integrated technologies. Technology scaling is the primary strategy implemented throughout the semiconductor industry to increase NVM density and drive down average cost per bit. In this paper, critical reliability challenges and key innovative technical mitigation methods are reviewed. TON is one of the major candidates to replace conventional oxide layer for its superior quality and reliability performance. Major advantages and caveats of key TON process techniques are discussed. The impact of TON on quality and reliability performance of charge storage NVM devices is carefully reviewed with emphasis on major advantages and drawbacks of top and bottom nitridation. Physical mechanisms attributed to charge retention and V(t) instability phenomenon are also reviewed in this paper.

Fast decision tree-based method to index large DNA-protein sequence databases using hybrid distributed-shared memory programming model

In recent times, the size of biological databases has increased significantly, with the continuous growth in the number of users and rate of queries; such that some databases have reached the terabyte size. There is therefore, the increasing need to access databases at the fastest rates possible. In this paper, the decision tree indexing model (PDTIM) was parallelised, using a hybrid of distributed and shared memory on resident database; with horizontal and vertical growth through Message Passing Interface (MPI) and POSIX Thread (PThread), to accelerate the index building time. The PDTIM was implemented using 1, 2, 4 and 5 processors on 1, 2, 3 and 4 threads respectively. The results show that the hybrid technique improved the speedup, compared to a sequential version. It could be concluded from results that the proposed PDTIM is appropriate for large data sets, in terms of index building time.

Recombinant protein-based nanoscale biomemory devices

Biomolecular computing devices that are based on the properties of biomolecular activities offer a unique possibility for constructing new computing structures. A new concept of using various biomolecules has been proposed in order to develop a protein-based memory device that is capable of switching physical properties when electrical input signals are applied to perform memory switching. To clarify the proposed concept, redox protein is immobilized on Au nanoelectrodes to catalyze reversible reactions of redox-active molecules, which is controlled electrochemically and reversibly converted between its ON/OFF states. In this review, we summarize recent research towards developing nanoscale biomemory devices including design, synthesis, fabrication, and functionalization based on the proposed concept. At first we analyze the memory function properties of the proposed device at bulk material level and then explain the WORM (write-once-read-many times) nature of the device, later we extend the analysis to multi-bit and multi-level storage functions, and then we focus the developments in nanoscale biomemory devices based on the electron transport of redox molecules to the underlying Au patterned surface. The developed device operates at very low voltages and has good stability and excellent reversibility, proving to be a promising platform for future memory devices.

Implementing capon beamforming on a GPU for real-time cardiac ultrasound imaging

Capon beamforming is associated with a high computational complexity, which limits its use as a real-time method in many applications. In this paper, we present an implementation of the Capon beamformer that exhibits realtime performance when applied in a typical cardiac ultrasound imaging setting. To achieve this performance, we make use of the parallel processing power found in modern graphics processing units (GPUs), combined with beamspace processing to reduce the computational complexity as the number of array elements increases. For a three-dimensional beamspace, we show that processing rates supporting real-time cardiac ultrasound imaging are possible, meaning that images can be processed faster than the image acquisition rate for a wide range of parameters. Image quality is investigated in an in vivo cardiac data set. These results show that Capon beamforming is feasible for cardiac ultrasound imaging, providing images with improved lateral resolution both in element-space and beamspace.

Structural and magnetic features of oxygen inserted [Co-O/Pt]n multi-layer matrix for spin transfer torque memory applications

We describe the influence of inserted oxygen atoms on the structural and magnetic properties of a [Co/Pt]n multi-layer matrix. The correlation of magnetic properties with oxygen gas flow rate was studied as an alternative perpendicular medium in spin transfer torque magnetic random access memory applications. Experimental analysis suggests that the addition of a small amount of oxygen atoms into the [Co/Pt]n multi-layer matrix leads to a high coercivity and proper magnetization performance, together with high thermal stability. Finally, the nature of the improved perpendicular medium behaviors is also discussed.

Generic relevance of counter charges for cation-based nanoscale resistive switching memories

Resistive switching memories (ReRAMs) are the major candidates for replacing the state-of-the-art memory technology in future nanoelectronics. These nonvolatile memory cells are based on nanoionic redox processes and offer prospects for high scalability, ultrafast write and read access, and low power consumption. The interfacial electrochemical reactions of oxidation and reduction of ions necessarily needed for resistive switching result inevitably in nonequilibrium states, which play a fundamental role in the processes involved during device operation. We report on nonequilibrium states in SiO2-based ReRAMs being induced during the resistance transition. It is demonstrated that the formation of metallic cations proceeds in parallel to reduction of moisture, supplied by the ambient. The latter results in the formation of an electromotive force in the range of up to 600 mV. The outcome of the study highlights the hitherto overlooked necessity of a counter charge/reaction to keep the charge electroneutrality in cation-transporting thin films, making it hard to analyze and compare experimental results under different ambient conditions such as water partial pressure. Together with the dependence of the electromotive force on the ambient, these results contribute to the microscopic understanding of the resistive switching phenomena in cation-based ReRAMs.

Transferable and flexible label-like macromolecular memory on arbitrary substrates with high performance and a facile methodology

A newly designed transferable and flexible label-like organic memory based on a graphene electrode behaves like a sticker, and can be readily placed on desired substrates or devices for diversified purposes. The memory label reveals excellent performance despite its physical presentation. This may greatly extend the memory applications in various advanced electronics and provide a simple scheme to integrate with other electronics.

Memristor-MOS analog correlator for pattern recognition system

Emergence of new materials having significant improved properties continues to influence the formulation of novel architectures and as such new developments pave the way for innovative circuits and systems such as those required in visual imaging and recognition systems. In this paper we introduce a novel approach for the design of an analog comparator suitable for pattern matching using two Memristors as part of both the stored image data as well as that of the input signal. Our proposed comparator based on Memristor-CMOS fabrication process generates a signal indicating similarity/dissimilarity between two pattern data derived from image sensor and the corresponding Memristor-based template memory. For convenience, we also present an overview of a simplified Memristor model and hence provide simulation results for comparison with that of a conventional analog CMOS comparator.

A pulse-frequency modulation sensor using memristive-based inhibitory interconnections

This paper proposes a programmable inhibitory interconnection network between pixels in an array of novel low-voltage Schmitt-trigger-based PFM sensors that will be of interest for future applications in memristor-based early vision processing. In addition, a new low-power inverter-based pulse-frequency modulation (PFM) design and its integration with the network is also presented. To ensure no change in the memristors conductance in the network, the CMOS imager was designed for low voltage operation. That has resulted in a significant power reduction, better than 60%, and a comparable linear dynamic range when compared to published designs in the literature. The design was performed using a 0.13 um Samsung Electronics standard CMOS process, using 0.75 V supply voltage.

Integrated memristor-MOS (M2) sensor for basic pattern matching applications

This paper introduces an integrated sensor circuit based on an analog Memristor-MOS (M2) pattern matching building block that calculates the similarity/dissimilarity between two analog values. A new approach for a pulse-width modulation pixel image sensor compatible with the memristive-MOS matching structure is introduced allowing direct comparison between incoming and stored images. The pulsed-width encoded information from the pixels is forwarded to a matching circuitry that provides an anti-Gaussian-like comparison between the states of memristors. The non-volatile and multi-state memory characteristics of memristor, together with the related ability to be programmed at any one of the intermediate states between logic '1' and logic '0' brings us closer to the implementation of bio-machines that can eventually emulate human-like sensory functions.

Memristor-based programmable logic array (PLA) and analysis as Memristive networks

A Memristor theorized by Chua in 1971 has the potential to dramatically influence the way electronic circuits are designed. It is a two terminal device whose resistance state is based on the history of charge flow brought about as the result of the voltage being applied across its terminals and hence can be thought of as a special case of a reconfigurable resistor. Nanoscale devices using dense and regular fabrics such as Memristor cross-bar is promising new architecture for System-on-Chip (SoC) implementations in terms of not only the integration density that the technology can offer but also both improved performance and reduced power dissipation. Memristor has the capacity to switch between high and low resistance states in a cross-bar circuit configuration. The cross-bars are formed from an array of vertical conductive nano-wires cross a second array of horizontal conductive wires. Memristors are realized at the intersection of the two wires in the array through appropriate processing technology such that any particular wire in the vertical array can be connected to a wire in the horizontal array by switching the resistance of a particular intersection to a low state while other cross-points remain in a high resistance state. However the approach introduces a number of challenges. The lack of voltage gain prevents logic being cascaded and voltage level degradation affects robustness of the operation. Moreover the cross-bars introduce sneak current paths when two or more cross points are connected through the switched Memristor. In this paper, we propose Memristor-based programmable logic array (PLA) architecture and develop an analytical model to analyze the logic level on the memristive networks. The proposed PLA architecture has 12 inputs maximum and can be cascaded for more input variables with R(off)/R(on) ratio in the range from 55 to 160 of Memristors.

A four-bit-per-cell program method with substrate-bias assisted hot electron injection for charge trap flash memory devices

We propose a four-bit-per-cell program method using a two-step sequence with substrate-bias assisted hot electron (SAHE) injection into the charge trap flash memory devices in order to overcome the limitations of conventional four-bit program methods, which use channel hot electron (CHE) injection. With this proposed method, a localized charge injection near the junction edge with an acceptable read margin was clearly observed, along with a threshold voltage difference of 1 V between the forward and the reverse read. In addition, a multi-level storage was easily obtained using a drain voltage step of 1 V at each level of the three programmed states, along with a fast program time of 1 micros. Finally, by using charge pumping methods, we directly observed the detailed information on the spatial distribution of the local threshold voltage in each level of the four states, for each physical bit, as a function of the program voltage.

Analysis of flicker noise for improved data retention characteristics in silicon-oxide-high-k-oxide-silicon flash memory using N2 implantation

In this paper, we fabricate planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and the planar-type SOHOS devices with N2 implantation of 3 x 10(15) dose in a tunneling oxide to determine the impact of N2 implantation in the tunneling oxide of a memory device. The N2 implantation device has better retention characteristics than the device with no implantation. In order establish the correlation between N2 implantation and retention characteristic improvement, the low frequency noise (1/f noise) characteristic is investigated. The normalized drain current noise (S(ID)/I(D)2) level of the N2 implantation device is higher than that of the device with no implantation, which means that N2 implantation causes more trap formation near the interface. Considering that N2 implantation does not affect the DC transfer characteristics, such as mobility and sub-threshold slope, this finding indicates that the increase in the 1/f noise level is due to oxide traps rather than to interface traps. Therefore, the retention characteristic improvement in the N2 implantation device can be explained by the generation of higher number of oxide traps and an increase in the potential barrier blocking the leakage path in the tunneling oxide.

Nitrogen-doped partially reduced graphene oxide rewritable nonvolatile memory

As memory materials, two-dimensional (2D) carbon materials such as graphene oxide (GO)-based materials have attracted attention due to a variety of advantageous attributes, including their solution-processability and their potential for highly scalable device fabrication for transistor-based memory and cross-bar memory arrays. In spite of this, the use of GO-based materials has been limited, primarily due to uncontrollable oxygen functional groups. To induce the stable memory effect by ionic charges of a negatively charged carboxylic acid group of partially reduced graphene oxide (PrGO), a positively charged pyridinium N that served as a counterion to the negatively charged carboxylic acid was carefully introduced on the PrGO framework. Partially reduced N-doped graphene oxide (PrGODMF) in dimethylformamide (DMF) behaved as a semiconducting nonvolatile memory material. Its optical energy band gap was 1.7-2.1 eV and contained a sp2 C═C framework with 45-50% oxygen-functionalized carbon density and 3% doped nitrogen atoms. In particular, rewritable nonvolatile memory characteristics were dependent on the proportion of pyridinum N, and as the proportion of pyridinium N atom decreased, the PrGODMF film lost memory behavior. Polarization of charged PrGODMF containing pyridinium N and carboxylic acid under an electric field produced N-doped PrGODMF memory effects that followed voltage-driven rewrite-read-erase-read processes.

Nonvolatile memory cells based on MoS2/graphene heterostructures

Memory cells are an important building block of digital electronics. We combine here the unique electronic properties of semiconducting monolayer MoS2 with the high conductivity of graphene to build a 2D heterostructure capable of information storage. MoS2 acts as a channel in an intimate contact with graphene electrodes in a field-effect transistor geometry. Our prototypical all-2D transistor is further integrated with a multilayer graphene charge trapping layer into a device that can be operated as a nonvolatile memory cell. Because of its band gap and 2D nature, monolayer MoS2 is highly sensitive to the presence of charges in the charge trapping layer, resulting in a factor of 10(4) difference between memory program and erase states. The two-dimensional nature of both the contact and the channel can be harnessed for the fabrication of flexible nanoelectronic devices with large-scale integration.

Speckle-free digital holographic recording of a diffusely reflecting object

We demonstrate holographic recording without speckle noise using the digital holographic technique called optical scanning holography (OSH). First, we record a complex hologram of a diffusely reflecting (DR) object using OSH. The incoherent mode of OSH makes it possible to record the complex hologram without speckle noise. Second, we convert the complex hologram to an off-axis real hologram digitally and finally we reconstruct the real hologram using an amplitude-only spatial light modulator (SLM) without twin-image noise and speckle noise. To the best of our knowledge, this is the first time demonstrating digital holographic recording of a DR object without speckle noise.