Coherent Hole Transport in Selective Area Grown Ge Nanowire Networks

Control of Ge island coalescence for the formation of nanowires on silicon

Germanium nanowires could be the building blocks of hole-spin qubit quantum computers. Selective area epitaxy enables the direct integration of Ge nanowires on a silicon chip while controlling the device design, density, and scalability. For this to become a reality, it is essential to understand and control the initial stages of the epitaxy process. In this work, we highlight the importance of surface treatment in the reactor prior to growth to achieve high crystal quality and connected Ge nanowire structures. In particular, we demonstrate that exposure to AsH3 during the high-temperature treatment enhances lateral growth of initial Ge islands and promotes faster formation of continuous Ge nanowires in trenches. The Kolmogorov-Johnson-Mehl-Avrami crystallization model supports our explanation of Ge coalescence. These results provide critical insight into the selective epitaxy of horizontal Ge nanowires on lattice-mismatched Si substrates, which can be translated to other material systems.

Electronic Transport and Quantum Phenomena in Nanowires

Nanowires are natural one-dimensional channels and offer new opportunities for advanced electronic quantum transport experiments. We review recent progress on the synthesis of nanowires and methods for the fabrication of hybrid semiconductor/superconductor systems. We discuss methods to characterize their electronic properties in the context of possible future applications such as topological and spin qubits. We focus on group III-V (InAs and InSb) and group IV (Ge/Si) semiconductors, since these are the most developed, and give an outlook on other potential materials.

Can Nanowires Coalesce?

Coalescence of nanowires and other three-dimensional structures into continuous film is desirable for growing low-dislocation-density III-nitride and III-V materials on lattice-mismatched substrates; this is also interesting from a fundamental viewpoint. Here, we develop a growth model for vertical nanowires which, under rather general assumptions on the solid-like coalescence process within the Kolmogorov crystallization theory, results in a morphological diagram for the asymptotic coverage of a substrate surface. The coverage is presented as a function of two variables: the material collection efficiency on the top nanowire facet a and the normalized surface diffusion flux of adatoms from the NW sidewalls b. The full coalescence of nanowires is possible only when a=1, regardless of b. At a>1, which often holds for vapor-liquid-solid growth with a catalyst droplet, nanowires can only partly merge but never coalesce into continuous film. In vapor phase epitaxy techniques, the NWs can partly merge but never fully coalesce, while in the directional molecular beam epitaxy the NWs can fully coalesce for small enough contact angles of their droplets corresponding to a=1. The growth kinetics of nanowires and evolution of the coverage in the pre-coalescence stage is also considered. These results can be used for predicting and controlling the degree of surface coverage by nanowires and three-dimensional islands by tuning the surface density, droplet size, adatoms diffusivity, and geometry of the initial structures in the vapor-liquid-solid, selective area, or self-induced growth by different epitaxy techniques.

The implementation of thermal and UV nanoimprint lithography for selective area epitaxy

Semiconductor nanowires (NWs) in horizontal configuration could provide a path for scalable NW-based devices. Bottom-up large-scale manufacturing of these nanostructures by selective area epitaxy (SAE) relies on precise nanopatterning of various shapes on the growth masks. Electron beam lithography offers an extraordinary accuracy suited for the purpose. However, this technique is not economically viable for large production as it has a low throughput and requires high investment and operational costs. Nanoimprint lithography (NIL) has the potential to reduce fabrication time and costs significantly while requiring less sophisticated equipment. In this work, we utilize both thermal and UV NIL for patterning substrates for SAE, elucidating the advantages and disadvantages of each lithography technique. We demonstrate the epitaxial growth of Ge and GaAs NWs on these substrates, where we observe high-quality mono-crystalline structures. Even though both processes can produce small uniform structures suitable for SAE, our results show that UV NIL proves to be superior and enables reliable and efficient patterning of sub-100 nm mask features at the wafer scale.

Trapping Layers Prevent Dopant Segregation and Enable Remote Doping of Templated Self-Assembled InGaAs Nanowires

Selective area epitaxy is a promising approach to define nanowire networks for topological quantum computing. However, it is challenging to concurrently engineer nanowire morphology, for carrier confinement, and precision doping, to tune carrier density. We report a strategy to promote Si dopant incorporation and suppress dopant diffusion in remote doped InGaAs nanowires templated by GaAs nanomembrane networks. Growth of a dilute AlGaAs layer following doping of the GaAs nanomembrane induces incorporation of Si that otherwise segregates to the growth surface, enabling precise control of the spacing between the Si donors and the undoped InGaAs channel; a simple model captures the influence of Al on the Si incorporation rate. Finite element modeling confirms that a high electron density is produced in the channel.

Strain-induced ordered Ge(Si) hut wires on patterned Si (001) substrates

Ge/Si nanowires are predicted to be a promising platform for spin and even topological qubits. While for large-scale integration of these devices, nanowires with fully controlled positions and arrangements are a prerequisite. Here, we have reported ordered Ge hut wires by multilayer heteroepitaxy on patterned Si (001) substrates. Self-assembled GeSi hut wire arrays are orderly grown inside patterned trenches with post growth surface flatness. Such embedded GeSi wires induce tensile strain on the Si surface, which results in preferential nucleation of Ge nanostructures. Ordered Ge nano-dashes, disconnected wires and continuous wires are obtained correspondingly by tuning the growth conditions. These site-controlled Ge nanowires on a flattened surface lead to the ease of fabrication and large-scale integration of nanowire quantum devices.