Surface State Dynamics Dictating Transport in InAs Nanowires

Large Memory Window of van der Waals Heterostructure Devices Based on MOCVD-Grown 2D Layered Ge4 Se9

Van der Waals (vdW) heterostructures have drawn much interest over the last decade owing to their absence of dangling bonds and their intriguing low-dimensional properties. The emergence of 2D materials has enabled the achievement of significant progress in both the discovery of physical phenomena and the realization of superior devices. In this work, the group IV metal chalcogenide 2D-layered Ge₄ Se₉ is introduced as a new selection of insulating vdW material. 2D-layered Ge₄ Se₉ is synthesized with a rectangular shape using the metalcorganic chemical vapor deposition system using a liquid germanium precursor at 240 °C. By stacking the Ge₄ Se₉ and MoS₂ , vdW heterostructure devices are fabricated with a giant memory window of 129 V by sweeping back gate range of ±80 V. The gate-independent decay time reveals that the large hysteresis is induced by the interfacial charge transfer, which originates from the low band offset. Moreover, repeatable conductance changes are observed over the 2250 pulses with low non-linearity values of 0.26 and 0.95 for potentiation and depression curves, respectively. The energy consumption of the MoS₂ /Ge₄ Se₉ device is about 15 fJ for operating energy and the learning accuracy of image classification reaches 88.3%, which further proves the great potential of artificial synapses.

Andreev Interference in the Surface Accumulation Layer of Half-Shell InAsSb/Al Hybrid Nanowires

Understanding the spatial distribution of charge carriers in III-V nanowires proximity coupled to superconductors is important for the design and interpretation of experiments based on hybrid quantum devices. In this letter, the gate-dependent surface accumulation layer of half-shell InAsSb/Al nanowires is studied by means of Andreev interference in a parallel magnetic field. Both uniform hybrid nanowires and devices featuring a short Josephson junction fabricated by shadow lithography, exhibit periodic modulation of the switching current. The period corresponds to a flux quantum through the nanowire diameter and is consistent with Andreev bound states occupying a cylindrical surface accumulation layer. The spatial distribution is tunable by a gate potential as expected from electrostatic models.

Semiconductor Nanowire Field-Effect Transistors as Sensitive Detectors in the Far-Infrared

Engineering detection dynamics in nanoscale receivers that operate in the far infrared (frequencies in the range 0.1-10 THz) is a challenging task that, however, can open intriguing perspectives for targeted applications in quantum science, biomedicine, space science, tomography, security, process and quality control. Here, we exploited InAs nanowires (NWs) to engineer antenna-coupled THz photodetectors that operated as efficient bolometers or photo thermoelectric receivers at room temperature. We controlled the core detection mechanism by design, through the different architectures of an on-chip resonant antenna, or dynamically, by varying the NW carrier density through electrostatic gating. Noise equivalent powers as low as 670 pWHz-1/2 with 1 µs response time at 2.8 THz were reached.

Gate Bias Stress Instability and Hysteresis Characteristics of InAs Nanowire Field-Effect Transistors

Because of the excellent electrical properties, III-V semiconductor nanowires are promising building blocks for next-generation electronics; however, their rich surface states inevitably contribute large amounts of charge traps, leading to gate bias stress instability and hysteresis characteristics in nanowire field-effect transistors (FETs). Here, we investigated thoroughly the gate bias stress and hysteresis effects in InAs nanowire FETs. It is observed that the output current decreases together with the threshold voltage shifting to the positive direction when a positive gate bias stress is applied, and vice versa for the negative gate bias stress. For double-sweep transfer characteristics, the significant hysteresis behavior is observed, depending heavily on the sweeping rate and range. On the basis of complementary investigations of these devices, charge traps are confirmed to be the dominant factor for these instability effects. Importantly, the hysteresis can be simulated well by utilizing a combination of the rate equation for electron density and the empirical model for electron mobility. This provides an accurate evaluation of carrier mobility, which is in distinct contrast to the overestimation of mobility when using the transconductance for calculation. All these findings are important for understanding the charge trap dynamics to further enhance the device performance of nanowire FETs.

Ultrathin catalyst-free InAs nanowires on silicon with distinct 1D sub-band transport properties

Ultrathin InAs nanowires (NW) with a one-dimensional (1D) sub-band structure are promising materials for advanced quantum-electronic devices, where dimensions in the sub-30 nm diameter limit together with post-CMOS integration scenarios on Si are much desired. Here, we demonstrate two site-selective synthesis methods that achieve epitaxial, high aspect ratio InAs NWs on Si with ultrathin diameters below 20 nm. The first approach exploits direct vapor-solid growth to tune the NW diameter by interwire spacing, mask opening size and growth time. The second scheme explores a unique reverse-reaction growth by which the sidewalls of InAs NWs are thermally decomposed under controlled arsenic flux and annealing time. Interesting kinetically limited dependencies between interwire spacing and thinning dynamics are found, yielding diameters as low as 12 nm for sparse NW arrays. We clearly verify the 1D sub-band structure in ultrathin NWs by pronounced conductance steps in low-temperature transport measurements using back-gated NW-field effect transistors. Correlated simulations reveal single- and double degenerate conductance steps, which highlight the rotational hexagonal symmetry and reproduce the experimental traces in the diffusive 1D transport limit. Modelling under the realistic back-gate configuration further evidences regimes that lead to asymmetric carrier distribution and breakdown of the degeneracy depending on the gate bias.

Interfacial Charge Transfer and Gate-Induced Hysteresis in Monochalcogenide InSe/GaSe Heterostructures

Heterostructures of two-dimensional (2D) van der Waals semiconductor materials offer a diverse playground for exploring fundamental physics and potential device applications. In InSe/GaSe heterostructures formed by sequential mechanical exfoliation and stacking of 2D monochalcogenides InSe and GaSe, we observe charge transfer between InSe and GaSe because of the 2D van der Waals interface formation and a strong hysteresis effect in the electron transport through the InSe layer when a gate voltage is applied through the GaSe layer. A gate voltage-dependent conductance decay rate is also observed. We relate these observations to the gate voltage-dependent dynamical charge transfer between InSe and GaSe layers.

Rethinking the Characterization of Nanoscale Field-Effect Transistors: A Universal Approach

Standard methods for calculating transport parameters in nanoscale field-effect transistors (FETs), namely carrier concentration and mobility, require a linear connection between the gate voltage and channel conductance; however, this is often not the case. One reason often overlooked is that shifts in chemical and electric potential can partially compensate each other, commonly referred to as quantum capacitance. In nanoscale FETs, capacitance is often unmeasurable and an analytical formula is required, which assumes the conducting channel as metallic and common methods of determining threshold voltage no longer couple properly into transport equations. As present and future FET structures become smaller and have increased channel-gate coupling, this issue will render standard methods impossible to use. This work discusses the validity of common methods of characterization for nanoscale FETs, develops a universal model to determine transport properties by only measuring the threshold voltage of an FET and presents a new parameter to easily classify FETs as either quantum capacitance-limited or metallic approximated charge transport. Also considered in this work is electrical hysteresis from trap states and, in combination with the proposed universal model, novel techniques are introduced to measure and remove the errors associated with these effects often ignored in literature.

Nonlinear Chemical Sensitivity Enhancement of Nanowires in the Ultralow Concentration Regime

Much recent attention has been focused on the development of field-effect transistors based on low-dimensional nanostructures for the detection and manipulation of molecules. Because of their extraordinarily high charge sensitivity, InAs nanowires present an excellent material system in which to probe and study the behavior of molecules on their surfaces and elucidate the underlying mechanisms dictating the sensor response. So far, chemical sensors have relied on slow, activated processes restricting their applicability to high temperatures and macroscopic adsorbate coverages. Here, we identify the transition into a highly sensitive regime of chemical sensing at ultralow concentrations (<1 ppm) via physisorption at room temperature using field-effect transistors with channels composed of several thousand InAs nanowires and ethanol as a simple analyte molecule. In this regime, the nanowire conductivity is dictated by a local gating effect from individual dipoles, leading to a nonlinear enhancement of the sensitivity. At higher concentrations (>1 ppm), the nanowire channel is globally gated by a uniform dipole layer at the nanowire surface. The former leads to a dramatic increase in sensitivity due to weakened screening and the one-dimensional geometry of the nanowire. In this regime, we detect concentrations of ethanol vapor as low as 10 ppb, 100 times below the lowest concentrations previously reported. Furthermore, we demonstrate electrostatic control of the sensitivity and dynamic range of the InAs nanowire-based sensor and construct a unified model that accurately describes and predicts the sensor response over the tested concentration range (10 ppb to 10 ppm).

Conductometric Sensing with Individual InAs Nanowires

In this work, we isolate individual wurtzite InAs nanowires and fabricate electrical contacts at both ends, exploiting the single nanostructures as building blocks to realize two different architectures of conductometric sensors: (a) the nanowire is drop-casted onto-supported by-a SiO2/Si substrate, and (b) the nanowire is suspended at approximately 250 nm from the substrate. We test the source-drain current upon changes in the concentration of humidity, ethanol, and NO2, using synthetic air as a gas carrier, moving a step forward towards mimicking operational environmental conditions. The supported architecture shows higher response in the mid humidity range (50% relative humidity), with shorter response and recovery times and lower detection limit with respect to the suspended nanowire. These experimental pieces of evidence indicate a minor role of the InAs/SiO2 contact area; hence, there is no need for suspended nanostructures to improve the sensing performance. Moreover, the sensing capability of single InAs nanowires for detection of NO2 and ethanol in the ambient atmosphere is reported and discussed.

Suppressing the excess OFF-state current of short-channel InAs nanowire field-effect transistors by nanoscale partial-gate

The excess OFF-state current caused by band to band tunneling (BTBT) is a serious issue particularly in short-channel nanowire (NW) field-effect transistors (FETs), especially for narrow bandgap semiconductors such as InAs. Here, to clarify the components of the OFF-current and suppress the OFF-current, we for the first time fabricate and study InAs NW FETs with nanoscale partial-gate (PG). We fabricate a series of PGFETs and a normal full-gate (FG) FET on the same NW. Based on our results, the BTBT current component can reach tens of nanoamps in a typical 250 nm-channel InAs NW FGFET, and dominate the OFF-current. In contrast, there is almost no BTBT component in the PGFET, which provides a reference for other short-channel InAs NW FETs. Furthermore, the physical mechanism of the OFF-state carrier transport is discussed, and both electrons and holes currents are proven to be very important, based on our experimental results. Also, through statistic study, we find the BTBT effect can be more serious in the devices with better gate-control. Therefore, suppressing the BTBT effect is important to the future scaling-down.