Fully "Erase-free" Multi-Bit Operation in HfO2-Based Resistive Switching Device

2Memristor-1Capacitor Integrated Temporal Kernel for High-Dimensional Data Mapping

Compact but precise feature-extracting ability is core to processing complex computational tasks in neuromorphic hardware. Physical reservoir computing (RC) offers a robust framework to map temporal data into a high-dimensional space using the time dynamics of a material system, such as a volatile memristor. However, conventional physical RC systems have limited dynamics for the given material properties, restricting the methods to increase their dimensionality. This study proposes an integrated temporal kernel composed of a 2-memristor and 1-capacitor (2M1C) using a W/HfO2/TiN memristor and TiN/ZrO2/Al2O3/ZrO2/TiN capacitor to achieve higher dimensionality and tunable dynamics. The kernel elements are carefully designed and fabricated into an integrated array, of which performances are evaluated under diverse conditions. By optimizing the time dynamics of the 2M1C kernel, each memristor simultaneously extracts complementary information from input signals. The MNIST benchmark digit classification task achieves a high accuracy of 94.3% with a (196×10) single-layer network. Analog input mapping ability is tested with a Mackey-Glass time series prediction, and the system records a normalized root mean square error of 0.04 with a 20×1 readout network, the smallest readout network ever used for Mackey-Glass prediction in RC. These performances demonstrate its high potential for efficient temporal data analysis.

Monolayer Vacancy-Induced MXene Memory for Write-Verify-Free Programming

The fundamental logic states of 1 and 0 in Complementary Metal-Oxide-Semiconductor (CMOS) are essential for modern high-speed non-volatile solid-state memories. However, the accumulated storage signal in conventional physical components often leads to data distortion after multiple write operations. This necessitates a write-verify operation to ensure proper values within the 0/1 threshold ranges. In this work, a non-gradual switching memory with two distinct stable resistance levels is introduced, enabled by the asymmetric vertical structure of monolayer vacancy-induced oxidized Ti3C2Tx MXene for efficient carrier trapping and releasing. This non-cumulative resistance effect allows non-volatile memories to attain valid 0/1 logic levels through direct reprogramming, eliminating the need for a write-verify operation. The device exhibits superior performance characteristics, including short write/erase times (100 ns), a large switching ratio (≈3 × 104), long cyclic endurance (>104 cycles), extended retention (>4 × 106 s), and highly resistive stability (>104 continuous write operations). These findings present promising avenues for next-generation resistive memories, offering faster programming speed, exceptional write performance, and streamlined algorithms.

Purely self-rectifying memristor-based passive crossbar array for artificial neural network accelerators

Memristor-integrated passive crossbar arrays (CAs) could potentially accelerate neural network (NN) computations, but studies on these devices are limited to software-based simulations owing to their poor reliability. Herein, we propose a self-rectifying memristor-based 1 kb CA as a hardware accelerator for NN computations. We conducted fully hardware-based single-layer NN classification tasks involving the Modified National Institute of Standards and Technology database using the developed passive CA, and achieved 100% classification accuracy for 1500 test sets. We also investigated the influences of the defect-tolerance capability of the CA, impact of the conductance range of the integrated memristors, and presence or absence of selection functionality in the integrated memristors on the image classification tasks. We offer valuable insights into the behavior and performance of CA devices under various conditions and provide evidence of the practicality of memristor-integrated passive CAs as hardware accelerators for NN applications.

Multi-level resistive switching in hafnium-oxide-based devices for neuromorphic computing

In the growing area of neuromorphic and in-memory computing, there are multiple reviews available. Most of them cover a broad range of topics, which naturally comes at the cost of details in specific areas. Here, we address the specific area of multi-level resistive switching in hafnium-oxide-based devices for neuromorphic applications and summarize the progress of the most recent years. While the general approach of resistive switching based on hafnium oxide thin films has been very busy over the last decade or so, the development of hafnium oxide with a continuous range of programmable states per device is still at a very early stage and demonstrations are mostly at the level of individual devices with limited data provided. On the other hand, it is positive that there are a few demonstrations of full network implementations. We summarize the general status of the field, point out open questions, and provide recommendations for future work.

Thin-film design of amorphous hafnium oxide nanocomposites enabling strong interfacial resistive switching uniformity

A design concept of phase-separated amorphous nanocomposite thin films is presented that realizes interfacial resistive switching (RS) in hafnium oxide-based devices. The films are formed by incorporating an average of 7% Ba into hafnium oxide during pulsed laser deposition at temperatures ≤400°C. The added Ba prevents the films from crystallizing and leads to ∼20-nm-thin films consisting of an amorphous HfO_x host matrix interspersed with ∼2-nm-wide, ∼5-to-10-nm-pitch Ba-rich amorphous nanocolumns penetrating approximately two-thirds through the films. This restricts the RS to an interfacial Schottky-like energy barrier whose magnitude is tuned by ionic migration under an applied electric field. Resulting devices achieve stable cycle-to-cycle, device-to-device, and sample-to-sample reproducibility with a measured switching endurance of ≥10⁴ cycles for a memory window ≥10 at switching voltages of ±2 V. Each device can be set to multiple intermediate resistance states, which enables synaptic spike-timing-dependent plasticity. The presented concept unlocks additional design variables for RS devices.

Time-varying data processing with nonvolatile memristor-based temporal kernel

Recent advances in physical reservoir computing, which is a type of temporal kernel, have made it possible to perform complicated timing-related tasks using a linear classifier. However, the fixed reservoir dynamics in previous studies have limited application fields. In this study, temporal kernel computing was implemented with a physical kernel that consisted of a W/HfO2/TiN memristor, a capacitor, and a resistor, in which the kernel dynamics could be arbitrarily controlled by changing the circuit parameters. After the capability of the temporal kernel to identify the static MNIST data was proven, the system was adopted to recognize the sequential data, ultrasound (malignancy of lesions) and electrocardiogram (arrhythmia), that had a significantly different time constant (10-7 vs. 1 s). The suggested system feasibly performed the tasks by simply varying the capacitance and resistance. These functionalities demonstrate the high adaptability of the present temporal kernel compared to the previous ones.

Self-rectifying resistive memory in passive crossbar arrays

Conventional computing architectures are poor suited to the unique workload demands of deep learning, which has led to a surge in interest in memory-centric computing. Herein, a trilayer (Hf0.8Si0.2O2/Al2O3/Hf0.5Si0.5O2)-based self-rectifying resistive memory cell (SRMC) that exhibits (i) large selectivity (ca. 104), (ii) two-bit operation, (iii) low read power (4 and 0.8 nW for low and high resistance states, respectively), (iv) read latency (<10 μs), (v) excellent non-volatility (data retention >104 s at 85 °C), and (vi) complementary metal-oxide-semiconductor compatibility (maximum supply voltage ≤5 V) is introduced, which outperforms previously reported SRMCs. These characteristics render the SRMC highly suitable for the main memory for memory-centric computing which can improve deep learning acceleration. Furthermore, the low programming power (ca. 18 nW), latency (100 μs), and endurance (>106) highlight the energy-efficiency and highly reliable random-access memory of our SRMC. The feasible operation of individual SRMCs in passive crossbar arrays of different sizes (30 × 30, 160 × 160, and 320 × 320) is attributed to the large asymmetry and nonlinearity in the current-voltage behavior of the proposed SRMC, verifying its potential for application in large-scale and high-density non-volatile memory for memory-centric computing.