Monolithic 3D integration of 2D materials-based electronics towards ultimate edge computing solutions

Van der Waals polarity-engineered 3D integration of 2D complementary logic

Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis1-3. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures4,5, as well as hetero-2D layers with different carrier types6-8, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs. 9-17) and MoS2 (refs. 11,18-28)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm2 V-1 s-1, on/off ratios reaching 106 and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.

Integration of MoS2 Memtransistor Devices and Analogue Circuits for Sensor Fusion in Autonomous Vehicle Target Localization

In contemporary autonomous driving systems relying on sensor fusion, traditional digital processors encounter challenges associated with analogue-to-digital conversion and iterative vector-matrix operations, which are encumbered by limitations in terms of response time and energy consumption. In this study, we present an analogue Kalman filter circuit based on molybdenum disulfide (MoS2) memtransistor, designed to accelerate sensor fusion for precise localization in autonomous vehicle applications. The nonvolatile memory characteristics of the memtransistor allow for the storage of a fixed Kalman gain, which eliminates the data convergence and thus accelerates the processing speeds. Additionally, the modulation of multiple conductance states by the gate terminal enables fast adaptability to diverse autonomous driving scenarios by tuning multiple Kalman filter gains. Our proposed analogue Kalman filter circuit accurately estimates the position coordinates of target vehicles by fusing sensor data from light detection and ranging (LiDAR), millimeter-wave radar (Radar), and camera, and it successfully solves real-word problems in a signal-free crossroad intersection. Notably, our system achieves a 1000-fold improvement in energy efficiency compared to that of digital circuits. This work underscores the viability of a memtransistor for achieving fast, energy-efficient real-time sensing, and continuous signal processing in advanced sensor fusion technology.

Monolithic three-dimensional tier-by-tier integration via van der Waals lamination

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1-10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11-13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.

In Situ Monitoring and Tuning Multilayer Stacking of Polymer Lamellar Crystals in Solution with Aggregation-Induced Emission

Many types of self-assembled 2D materials with fascinating morphologies and novel properties have been prepared and used in solution. However, it is still a challenge to monitor their in situ growth in solution and to control the number of layers in these materials. Here, we demonstrate that the aggregation-induced emission (AIE) effect can be applied for the in situ decoupled tracing of the lateral growth and multilayer stacking of polymer lamellar crystals in solution. Multilayer stacking considerably enhances the photoluminescence intensity of the AIE molecules sandwiched between two layers of lamellar crystals, which is 2.4 times that on the surface of monolayer crystals. Both variation of the self-seeding temperature of crystal seeds and addition of a trace amount of long polymer chains during growth can control multilayer lamellar stacking, which are applied to produce tunable fluorescent patterns for functional applications.

Junctionless Negative-Differential-Resistance Device Using 2D Van-Der-Waals Layered Materials for Ternary Parallel Computing

Negative-differential-resistance (NDR) devices offer a promising pathway for developing future computing technologies characterized by exceptionally low energy consumption, especially multivalued logic computing. Nevertheless, conventional approaches aimed at attaining the NDR phenomenon involve intricate junction configurations and/or external doping processes in the channel region, impeding the progress of NDR devices to the circuit and system levels. Here, an NDR device is presented that incorporates a channel without junctions. The NDR phenomenon is achieved by introducing a metal-insulator-semiconductor capacitor to a portion of the channel area. This approach establishes partial potential barrier and well that effectively restrict the movement of hole and electron carriers within specific voltage ranges. Consequently, this facilitates the implementation of both a ternary inverter and a ternary static-random-access-memory, which are essential components in the development of multivalued logic computing technology.