High-Gain Graphene Transistors with a Thin AlOx Top-Gate Oxide

Probing charge traps at the 2D semiconductor/dielectric interface

The family of 2-dimensional (2D) semiconductors is a subject of intensive scientific research due to their potential in next-generation electronics. While offering many unique properties like atomic thickness and chemically inert surfaces, the integration of 2D semiconductors with conventional dielectric materials is challenging. The charge traps at the semiconductor/dielectric interface are among many issues to be addressed before these materials can be of industrial relevance. Conventional electrical characterization methods remain inadequate to quantify the traps at the 2D semiconductor/dielectric interface since the estimations of the density of interface traps, Dit, by different techniques may yield more than an order-of-magnitude discrepancy, even when extracted from the same device. Therefore, the challenge to quantify Dit at the 2D semiconductor/dielectric interface is about finding an accurate and reliable measurement method. In this review, we discuss characterization techniques which have been used to study the 2D semiconductor/dielectric interface. Specifically, we discuss the methods based on small-signal AC measurements, subthreshold slope measurements and low-frequency noise measurements. While these approaches were developed for silicon-based technology, 2D semiconductor devices possess a set of unique challenges requiring a careful re-evaluation when using these characterization techniques. We examine the conventional methods based on their efficacy and accuracy in differentiating various types of trap states and provide guidance to find an appropriate method for charge trap analysis and estimation of Dit at 2D semiconductor/dielectric interfaces.

Compact Modeling Technology for the Simulation of Integrated Circuits Based on Graphene Field-Effect Transistors

The progress made toward the definition of a modular compact modeling technology for graphene field-effect transistors (GFETs) that enables the electrical analysis of arbitrary GFET-based integrated circuits is reported. A set of primary models embracing the main physical principles defines the ideal GFET response under DC, transient (time domain), AC (frequency domain), and noise (frequency domain) analysis. Another set of secondary models accounts for the GFET non-idealities, such as extrinsic-, short-channel-, trapping/detrapping-, self-heating-, and non-quasi static-effects, which can have a significant impact under static and/or dynamic operation. At both device and circuit levels, significant consistency is demonstrated between the simulation output and experimental data for relevant operating conditions. Additionally, a perspective of the challenges during the scale up of the GFET modeling technology toward higher technology readiness levels while drawing a collaborative scenario among fabrication technology groups, modeling groups, and circuit designers, is provided.

Graphene-Based Microwave Circuits: A Review

Over the past two decades, research on 2D materials has received much interest. Graphene is the most promising candidate regarding high-frequency applications thus far due to is high carrier mobility. Here, the research about the employment of graphene in micro- and millimeter-wave circuits is reviewed. The review starts with the different methodologies to grow and transfer graphene, before discussing the way graphene-based field-effect-transistors (GFETs) and diodes are built. A review on different approaches for realizing these devices is provided before discussing the employment of both GFETs and graphene diodes in different micro- and millimeter-wave circuits, showing the possibilities but also the limitations of this 2D material for high-frequency applications.

2D Electronics Based on Graphene Field Effect Transistors: Tutorial for Modelling and Simulation

This paper provides modeling and simulation insights into field-effect transistors based on graphene (GFET), focusing on the devices' architecture with regards to the position of the gate (top-gated graphene transistors, back-gated graphene transistors, and top-/back-gated graphene transistors), substrate (silicon, silicon carbide, and quartz/glass), and the graphene growth (CVD, CVD on SiC, and mechanical exfoliation). These aspects are explored and discussed in order to facilitate the selection of the appropriate topology for system-level design, based on the most common topologies. Since most of the GFET models reported in the literature are complex and hard to understand, a model of a GFET was implemented and made available in MATLAB, Verilog in Cadence, and VHDL-AMS in Simplorer-useful tools for circuit designers with different backgrounds. A tutorial is presented, enabling the researchers to easily implement the model to predict the performance of their devices. In short, this paper aims to provide the initial knowledge and tools for researchers willing to use GFETs in their designs at the system level, who are looking to implement an initial setup that allows the inclusion of the performance of GFETs.

GFET Asymmetric Transfer Response Analysis through Access Region Resistances

Graphene-based devices are planned to augment the functionality of Si and III-V based technology in radio-frequency (RF) electronics. The expectations in designing graphene field-effect transistors (GFETs) with enhanced RF performance have attracted significant experimental efforts, mainly concentrated on achieving high mobility samples. However, little attention has been paid, so far, to the role of the access regions in these devices. Here, we analyse in detail, via numerical simulations, how the GFET transfer response is severely impacted by these regions, showing that they play a significant role in the asymmetric saturated behaviour commonly observed in GFETs. We also investigate how the modulation of the access region conductivity (i.e., by the influence of a back gate) and the presence of imperfections in the graphene layer (e.g., charge puddles) affects the transfer response. The analysis is extended to assess the application of GFETs for RF applications, by evaluating their cut-off frequency.

Growth of graphene with large single-crystal domains by Ni foam-assisted structure and its high-gain field-effect transistors

High-quality graphene materials and high-performance graphene transistors have attracted much attention in recent years. To obtain high-performance graphene transistors, large single-crystal graphene is needed. The synthesis of large-domain-sized single-crystal graphene requires low nucleation density; this can lead to a lower growth rate. In this study, a Ni-foam assisted structure was developed to control the nucleation density and growth rate of graphene by tuning the flow dynamics. Lower nucleation density and high growth rate (∼50 μm min^-1) were achieved with a 4 mm-gap Ni foam. With the graphene transistor fabrication process, a pre-deposited Au film as the protective layer was used during the graphene transfer. Graphene transistors showed good current saturation with drain differential conductance as low as 0.04 S mm^-1 in the strong saturation region. For the devices with gate length of 2 μm, the intrinsic cut-off frequency f _T and maximum oscillation frequency f _max were 8.4 and 16.3 GHz, respectively, with f _max/f _T = 1.9 and power gain of up to 6.4 dB at 1 GHz. The electron velocity saturation induced by the surface optical phonons of SiO₂ substrates was analyzed. Electron velocity saturation and ultra-thin Al₂O₃ gate dielectrics were thought to be the reasons for the good current saturation and high power gain of the graphene transistors.

Graphene-Si CMOS oscillators

Graphene field-effect transistors (GFETs) offer a possibility of exploiting unique physical properties of graphene in realizing novel electronic circuits. However, graphene circuits often lack the voltage swing and switchability of Si complementary metal-oxide-semiconductor (CMOS) circuits, which are the main building block of modern electronics. Here we introduce graphene in Si CMOS circuits to exploit favorable electronic properties of both technologies and realize a new class of simple oscillators using only a GFET, Si CMOS D latch, and timing RC circuit. The operation of the two types of realized oscillators is based on the ambipolarity of graphene, i.e., the symmetry of the transfer curve of GFETs around the Dirac point. The ambipolarity of graphene also allowed to turn the oscillators into pulse-width modulators (with a duty cycle ratio ∼1 : 4) and voltage-controlled oscillators (with a frequency ratio ∼1 : 8) without any circuit modifications. The oscillation frequency was in the range from 4 kHz to 4 MHz and limited only by the external circuit connections, rather than components themselves. The demonstrated graphene-Si CMOS hybrid circuits pave the way to the more widespread adoption of graphene in electronics.

High-Performance CVD Bernal-Stacked Bilayer Graphene Transistors for Amplifying and Mixing Signals at High Frequencies

Tunable bandgap can be induced in Bernal-stacked bilayer graphene by a perpendicularly electric displacement field. Here, we carry out a comprehensive study on the material synthesis of CVD Bernal-stacked bilayer graphene and devices for amplifying and mixing at high frequencies. The transistors show large output current density with excellent current saturation with high intrinsic voltage gain up to 77. Positive extrinsic forward power gain | S₂₁|² has been obtained up to 5.6 GHz as well as high conversion gain of -7 dB for the mixers. The conversion gain dependence on tunable on/off ratio of the transistors has also been discussed.