Effects of surface and twinning energies on twining-superlattice formation in group III-V semiconductor nanowires: a first-principles study

Direct Observations of Twin Formation Dynamics in Binary Semiconductors

With the increased demand for controlled deterministic growth of III-V semiconductors at the nanoscale, the impact and interest of understanding defect formation and crystal structure switching becomes increasingly important. Vapor-liquid-solid (VLS) growth of semiconductor nanocrystals is an important mechanism for controlling and studying the formation of individual crystal layers and stacking defects. Using in situ studies, combining atomic resolution of transmission electron microscopy and controlled VLS crystal growth using metal organic chemical vapor deposition, we investigate the simplest achievable change in atomic layer stacking-single twinned layers formed in GaAs. Using Au-assisted GaAs nanowires of various diameters, we study the formation of individual layers with atomic resolution to reveal the growth difference in forming a twin defect. We determine that the formation of a twinned layer occurs significantly more slowly than that of a normal crystal layer. To understand this, we conduct thermodynamic modeling and determine that the propagation of a twin is limited by the energy cost of forming the twin interface. Finally, we determine that the slower propagation of twinned layers increases the probability of additional layers nucleating, such that multiple layers grow simultaneously. This observation challenges the current understanding that continuous uniform epitaxial growth, especially in the case of liquid-metal assisted nanowires, proceeds one single layer at a time and that its progression is limited by the nucleation rate.

Formation Mechanism of Twinning Superlattices in Doped GaAs Nanowires

Recent investigations of III-V semiconductor nanowires have revealed periodic zinc-blende twins, known as twinning superlattices, that are often induced by a high-impurity dopant concentration. In the present study, the relationship between the nanowire morphology, crystal structure, and impurity dopant concentration (Te and Be) of twinning superlattices has been studied in GaAs nanowires grown by molecular beam epitaxy using the self-assisted (with a Ga droplet) vapor-liquid-solid process. The contact angle between the Ga droplet and the nanowire top facet decreased linearly with the dopant concentration, whereas the period of the twinning superlattices increased with the doping concentration and was proportional to the nanowire radius. Our model, which is based entirely on surface energetics, is able to explain a unified formation mechanism of twinning superlattices in doped semiconductor nanowires.

Nanowire Electronics: From Nanoscale to Macroscale

Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.