Reconfiguration of operation modes in silicon nanowire field-effect transistors by electrostatic virtual doping

Gate-bias stability of triple-gated feedback field-effect transistors with silicon nanosheet channels

In this study, we investigate the gate-bias stability of triple-gated feedback field-effect transistors (FBFETs) with Si nanosheet channels. The subthreshold swing (SS) of FBFETs increases from 0.3 mV dec-1to 60 and 80 mV dec-1inp- andn-channel modes, respectively, when a positive bias stress (PBS) is applied for 1000 s. In contrast, the SS value does not change even after a negative bias stress (NBS) is applied for 1000 s. The difference in the switching characteristics under PBS and NBS is attributed to the ability of the interface traps to readily gain electrons from the inversion layer. The switching characteristics deteriorated by PBS are completely recovered after annealing at 300 °C for 10 min, and the characteristics remain stable even after PBS is applied again for 1000 s.

Fabrication of Silicon Nanowires by Metal-Assisted Chemical Etching Combined with Micro-Vibration

In this work, we design a micro-vibration platform, which combined with the traditional metal-assisted chemical etching (MaCE) to etch silicon nanowires (SiNWs). The etching mechanism of SiNWs, including in the mass-transport (MT) and charge-transport (CT) processes, was explored through the characterization of SiNW's length as a function of MaCE combined with micro-vibration conditions, such as vibration amplitude and frequency. The scanning electron microscope (SEM) experimental results indicated that the etching rate would be continuously improved with an increase in amplitude and reached its maximum at 4 μm. Further increasing amplitude reduced the etching rate and affected the morphology of the SiNWs. Adjusting the vibration frequency would result in a maximum etching rate at a frequency of 20 Hz, and increasing the frequency will not help to improve the etching effects.

Buried graphene heterostructures for electrostatic doping of low-dimensional materials

The fabrication and characterization of steep slope transistor devices based on low-dimensional materials requires precise electrostatic doping profiles with steep spatial gradients in order to maintain maximum control over the channel. In this proof-of-concept study we present a versatile graphene heterostructure platform with three buried individually addressable gate electrodes. The platform is based on a vertical stack of embedded titanium and graphene separated by an intermediate oxide to provide an almost planar surface. We demonstrate the functionality and advantages of the platform by exploring transfer and output characteristics at different temperatures of carbon nanotube field-effect transistors with different electrostatic doping configurations. Furthermore, we back up the concept with finite element simulations to investigate the surface potential. The presented heterostructure is an ideal platform for analysis of electrostatic doping of low-dimensional materials for novel low-power transistor devices.