A low-power integrated bioamplifier with active low-frequency suppression

Magic of 5G Technology and Optimization Methods Applied to Biomedical Devices: A Survey

Wireless networks have gained significant attention and importance in healthcare as various medical devices such as mobile devices, sensors, and remote monitoring equipment must be connected to communication networks. In order to provide advanced medical treatments to patients, high-performance technologies such as the emerging fifth generation/sixth generation (5G/6G) are required for transferring data to and from medical devices and in addition to their major components developed with improved optimization methods which are substantially needed and embedded in them. Providing intelligent system design is a challenging task in medical applications, as it affects the whole behaviors of medical devices. A critical review of the medical devices and the various optimization methods employed are presented in this paper, to pave the way for designers to develop an apparatus that is applicable in the healthcare industry under 5G technology and future 6G wireless networks.

Light Modulation of Brain and Development of Relevant Equipment

Light modulation plays an important role in understanding the pathology of brain disorders and improving brain function. Optogenetic techniques can activate or silence targeted neurons with high temporal and spatial accuracy and provide precise control, and have recently become a method for quick manipulation of genetically identified types of neurons. Photobiomodulation (PBM) is light therapy that utilizes non-ionizing light sources, including lasers, light emitting diodes, or broadband light. It provides a safe means of modulating brain activity without any irreversible damage and has established optimal treatment parameters in clinical practice. This manuscript reviews 1) how optogenetic approaches have been used to dissect neural circuits in animal models of Alzheimer's disease, Parkinson's disease, and depression, and 2) how low level transcranial lasers and LED stimulation in humans improves brain activity patterns in these diseases. State-of-the-art brain machine interfaces that can record neural activity and stimulate neurons with light have good prospects in the future.

An introduction and review on innovative silicon implementations of implantable/scalp EEG chips for data acquisition, seizure/behavior detection, and brain stimulation

Technological advances in the semiconductor industry and the increasing demand and development of wearable medical systems have enabled the development of dedicated chips for complex electroencephalogram (EEG) signal processing with smart functions and artificial intelligence‐based detections/classifications. Around 10 million transistors are integrated into a 1 mm2 silicon wafer surface in the dedicated chip, making wearable EEG systems a powerful dedicated processor instead of a wireless raw data transceiver. The reduction of amplifiers and analog‐digital converters on the silicon surface makes it possible to place the analog front‐end circuits within a tiny packaged chip; therefore, enabling high‐count EEG acquisition channels. This article introduces and reviews the state‐of‐the‐art dedicated chip designs for EEG processing, particularly for wearable systems. Furthermore, the analog circuits and digital platforms are included, and the technical details of circuit topology and logic architecture are presented in detail.

A Review of Microelectronic Systems and Circuit Techniques for Electrical Neural Recording Aimed at Closed-Loop Epilepsy Control

Closed-loop implantable electronics offer a new trend in therapeutic systems aimed at controlling some neurological diseases such as epilepsy. Seizures are detected and electrical stimulation applied to the brain or groups of nerves. To this aim, the signal recording chain must be very carefully designed so as to operate in low-power and low-latency, while enhancing the probability of correct event detection. This paper reviews the electrical characteristics of the target brain signals pertaining to epilepsy detection. Commercial systems are presented and discussed. Finally, the major blocks of the signal acquisition chain are presented with a focus on the circuit architecture and a careful attention to solutions to issues related to data acquisition from multi-channel arrays of cortical sensors.

Multi-Channel Neural Recording Implants: A Review

The recently growing progress in neuroscience research and relevant achievements, as well as advancements in the fabrication process, have increased the demand for neural interfacing systems. Brain-machine interfaces (BMIs) have been revealed to be a promising method for the diagnosis and treatment of neurological disorders and the restoration of sensory and motor function. Neural recording implants, as a part of BMI, are capable of capturing brain signals, and amplifying, digitizing, and transferring them outside of the body with a transmitter. The main challenges of designing such implants are minimizing power consumption and the silicon area. In this paper, multi-channel neural recording implants are surveyed. After presenting various neural-signal features, we investigate main available neural recording circuit and system architectures. The fundamental blocks of available architectures, such as neural amplifiers, analog to digital converters (ADCs) and compression blocks, are explored. We cover the various topologies of neural amplifiers, provide a comparison, and probe their design challenges. To achieve a relatively high SNR at the output of the neural amplifier, noise reduction techniques are discussed. Also, to transfer neural signals outside of the body, they are digitized using data converters, then in most cases, the data compression is applied to mitigate power consumption. We present the various dedicated ADC structures, as well as an overview of main data compression methods.

A Fully Implantable Wireless ECoG 128-Channel Recording Device for Human Brain-Machine Interfaces: W-HERBS

Brain-machine interfaces (BMIs) are promising devices that can be used as neuroprostheses by severely disabled individuals. Brain surface electroencephalograms (electrocorticograms, ECoGs) can provide input signals that can then be decoded to enable communication with others and to control intelligent prostheses and home electronics. However, conventional systems use wired ECoG recordings. Therefore, the development of wireless systems for clinical ECoG BMIs is a major goal in the field. We developed a fully implantable ECoG signal recording device for human ECoG BMI, i.e., a wireless human ECoG-based real-time BMI system (W-HERBS). In this system, three-dimensional (3D) high-density subdural multiple electrodes are fitted to the brain surface and ECoG measurement units record 128-channel (ch) ECoG signals at a sampling rate of 1 kHz. The units transfer data to the data and power management unit implanted subcutaneously in the abdomen through a subcutaneous stretchable spiral cable. The data and power management unit then communicates with a workstation outside the body and wirelessly receives 400 mW of power from an external wireless transmitter. The workstation records and analyzes the received data in the frequency domain and controls external devices based on analyses. We investigated the performance of the proposed system. We were able to use W-HERBS to detect sine waves with a 4.8-μV amplitude and a 60-200-Hz bandwidth from the ECoG BMIs. W-HERBS is the first fully implantable ECoG-based BMI system with more than 100 ch. It is capable of recording 128-ch subdural ECoG signals with sufficient input-referred noise (3 μVrms) and with an acceptable time delay (250 ms). The system contributes to the clinical application of high-performance BMIs and to experimental brain research.

An Adaptive Averaging Low Noise Front-End for Central and Peripheral Nerve Recording

An adaptive averaging low noise analog front-end (AFE) is presented for central and peripheral nerve recording applications. The proposed topology allows users to trade off, on the fly, between input referred noise and the number of channels via averaging. The new low noise amplifier (LNA) utilizes a complementary doubled input transconductance (g m ) topology to effectively increase the noise efficiency factor (NEF) without chopping or use of a costly BiCMOS process. It addresses a disadvantage of the doubled-g m technique by a high input impedance DC-coupled LNA and saves on-chip space for higher density by eliminating AC-coupling capacitors. The proposed technique is particularly suitable for ultra-low noise multichannel recording from the peripheral nervous system (PNS) with channel selection analog multiplexer, where input signal is in tens of μV. A 32-ch proof-of-concept-prototype AFE was fabricated in a 5M2P 130-nm standard CMOS process, occupying 2.4 × 2.5 mm2 together with its control block. The prototype LNA consumes 11 μW from a 1 V supply, providing 3.0 μVrms input referred noise with 61 ΜΩ input impedance, which are desirable for high SNR, to be further improved by the adaptive averaging technique.

High-Pass Converter Design Using a State-Space Approach and Its Application to Cardiac Signal Acquisition

Cardiac signal acquisition with high linearity and accuracy of the high-pass cut-off frequency imposes a challenge on the implementation of the analog preprocessing and the analog-to-digital converter. This paper describes a state-space-based methodology for designing high-pass sigma-delta (HP) topologies with high linearity, targeting high accuracy of the high-pass cut-off frequency. Intermediate functions are evaluated mathematically to compare the proposed HP topologies with respect to dynamic range. A sensitivity performance analysis of the noise transfer function with respect to integrator nonidealities and coefficient variations is also described. Finally, to illustrate the design approach, an orthonormal HP modulator is designed to be implemented in 0.18 m CMOS technology, is tested with real prerecorded ECG signals.

A Low-Power Current-Reuse Analog Front-End for High-Density Neural Recording Implants

Studying brain activity in vivo requires collecting bioelectrical signals from several microelectrodes simultaneously in order to capture neuron interactions. In this work, we present a new current-reuse analog front-end (AFE), which is scalable to very large numbers of recording channels, thanks to its small implementation silicon area and its low-power consumption. This current-reuse AFE, which is including a low-noise amplifier (LNA) and a programmable gain amplifier (PGA), employs a new fully differential current-mirror topology using fewer transistors, and improving several design parameters, such as power consumption and noise, over previous current-reuse amplifier circuit implementations. We show that the proposed current-reuse amplifier can provide a theoretical noise efficiency factor (NEF) as low as 1.01, which is the lowest reported theoretical NEF provided by an LNA topology. A foue-channel current-reuse AFE implemented in a CMOS 0.18-μm technology is presented as a proof-of-concept. T-network capacitive circuits are used to decrease the size of input capacitors and to increase the gain accuracy in the AFE. The measured performance of the whole AFE is presented. The total power consumption per channel, including the LNA and the PGA stage, is 9 μW (4.5 μW for LNA and 4.5 μW for PGA), for an input referred noise of 3.2 μV_rms, achieving a measured NEF of 1.94. The entire AFE presents three selectable gains of 35.04, 43.1, and 49.5 dB, and occupies a die area of 0.072 mm² per channel. The implemented circuit has a measured inter-channel rejection ratio of 54 dB. In vivo recording results obtained with the proposed AFE are reported. It successfully allows collecting low-amplitude extracellular action potential signals from a tungsten wire microelectrode implanted in the hippocampus of a laboratory mouse.

An Integrated Circuit for Simultaneous Extracellular Electrophysiology Recording and Optogenetic Neural Manipulation

OBJECTIVE

The ability to record and to control action potential firing in neuronal circuits is critical to understand how the brain functions. The objective of this study is to develop a monolithic integrated circuit (IC) to record action potentials and simultaneously control action potential firing using optogenetics.

METHODS

A low-noise and high input impedance (or low input capacitance) neural recording amplifier is combined with a high current laser/light-emitting diode (LED) driver in a single IC.

RESULTS

The low input capacitance of the amplifier (9.7 pF) was achieved by adding a dedicated unity gain stage optimized for high impedance metal electrodes. The input referred noise of the amplifier is [Formula: see text], which is lower than the estimated thermal noise of the metal electrode. Thus, the action potentials originating from a single neuron can be recorded with a signal-to-noise ratio of at least 6.6. The LED/laser current driver delivers a maximum current of 330 mA, which is adequate for optogenetic control. The functionality of the IC was tested with an anesthetized Mongolian gerbil and auditory stimulated action potentials were recorded from the inferior colliculus. Spontaneous firings of fifth (trigeminal) nerve fibers were also inhibited using the optogenetic protein Halorhodopsin. Moreover, a noise model of the system was derived to guide the design.

SIGNIFICANCE

A single IC to measure and control action potentials using optogenetic proteins is realized so that more complicated behavioral neuroscience research and the translational neural disorder treatments become possible in the future.

Miniaturized FDDA and CMOS Based Potentiostat for Bio-Applications

A novel fully differential difference CMOS potentiostat suitable for neurotransmitter sensing is presented. The described architecture relies on a fully differential difference amplifier (FDDA) circuit to detect a wide range of reduction-oxidation currents, while exhibiting low-power consumption and low-noise operation. This is made possible thanks to the fully differential feature of the FDDA, which allows to increase the source voltage swing without the need for additional dedicated circuitry. The FDDA also reduces the number of amplifiers and passive elements in the potentiostat design, which lowers the overall power consumption and noise. The proposed potentiostat was fabricated in 0.18 µm CMOS, with 1.8 V supply voltage. The device achieved 5 µA sensitivity and 0.99 linearity. The input-referred noise was 6.9 µV rms and the flicker noise was negligible. The total power consumption was under 55 µW. The complete system was assembled on a 20 mm × 20 mm platform that includes the potentiostat chip, the electrode terminals and an instrumentation amplifier for redox current buffering, once converted to a voltage by a series resistor. the chip dimensions were 1 mm × 0.5 mm and the other PCB components were off-chip resistors, capacitors and amplifiers for data acquisition. The system was successfully tested with ferricyanide, a stable electroactive compound, and validated with dopamine, a popular neurotransmitter.

Low-Frequency Noise and Offset Rejection in DC-Coupled Neural Amplifiers: A Review and Digitally-Assisted Design Tutorial

We review integrated circuits for low-frequency noise and offset rejection as a motivation for the presented digitally-assisted neural amplifier design methodology. Conventional AC-coupled neural amplifiers inherently reject input DC offset but have key limitations in area, linearity, DC drift, and spectral accuracy. Their chopper stabilization reduces low-frequency intrinsic noise at the cost of degraded area, input impedance and design complexity. DC-coupled implementations with digital high-pass filtering yield improved area, linearity, drift, and spectral accuracy and are inherently suitable for simple chopper stabilization. As a design example, a 56-channel 0.13 [Formula: see text] CMOS intracranial EEG interface is presented. DC offset of up to ±50 mV is rejected by a digital low-pass filter and a 16-bit delta-sigma DAC feeding back into the folding node of a folded-cascode LNA with CMRR of 65 dB. A bank of seven column-parallel fully differential SAR ADCs with ENOB of 6.6 are shared among 56 channels resulting in 0.018 [Formula: see text] effective channel area. Compensation-free direct input chopping yields integrated input-referred noise of 4.2 μV_rms over the bandwidth of 1 Hz to 1 kHz. The 8.7 [Formula: see text] chip dissipating 1.07 mW has been validated in vivo in online intracranial EEG monitoring in freely moving rats.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

A 512-channels, whole array readout, CMOS implantable probe for acute recordings from the brain

The integration of implantable CMOS neural probes with thousands of simultaneously recording microelectrodes is a promising approach for neuroscience and might allow to literally image electrophysiological neuronal activity in multiple brain circuits as we have previously shown in vitro. Here, we present a complete system based on a fully multiplexed CMOS neural probe that was designed for in-vivo acute recordings with a scalable circuit architecture. In particular, a first prototype of a single-shaft probe with 512 electrodes was realized in a standard CMOS 0.18μm technology and post-processed to structure the shaft with a wedge-like geometry of 30μm in thickness at the tip and 80μm at the base. The design of the system and of the probe as well as the post-processing techniques are discussed. Finally, preliminary results on electrical, mechanical and implantation tests are presented to demonstrate the feasibility of our approach.

A Low Noise Amplifier for Neural Spike Recording Interfaces

This paper presents a Low Noise Amplifier (LNA) for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between power, area and noise. Additionally, this work introduces a novel transistor-level synthesis methodology for LNAs tailored for the minimization of their noise efficiency factor under area and noise constraints. The proposed LNA has been implemented in a 130 nm CMOS technology and occupies 0.053 mm-sq. Experimental results show that the LNA offers a noise efficiency factor of 2.16 and an input referred noise of 3.8 μVrms for 1.2 V power supply. It provides a gain of 46 dB over a nominal bandwidth of 192 Hz–7.4 kHz and consumes 1.92 μW. The performance of the proposed LNA has been validated through in vivo experiments with animal models.

A DSP for sensing the bladder volume through afferent neural pathways

In this paper, we present a digital signal processor (DSP) capable of monitoring the urinary bladder volume through afferent neural pathways. The DSP carries out real-time detection and can discriminate extracellular action potentials, also known as on-the-fly spike sorting. Next, the DSP performs a decoding method to estimate either three qualitative levels of fullness or the bladder volume value, depending on the selected output mode. The proposed DSP was tested using both realistic synthetic signals with a known ground-truth, and real signals from bladder afferent nerves recorded during acute experiments with animal models. The spike sorting processing circuit yielded an average accuracy of 92% using signals with highly correlated spike waveforms and low signal-to-noise ratios. The volume estimation circuits, tested with real signals, reproduced accuracies achieved by offline simulations in Matlab, i.e., 94% and 97% for quantitative and qualitative estimations, respectively. To assess feasibility, the DSP was deployed in the Actel FPGA Igloo AGL1000V2, which showed a power consumption of 0.5 mW and a latency of 2.1 ms at a 333 kHz core frequency. These performance results demonstrate that an implantable bladder sensor that perform the detection, discrimination and decoding of afferent neural activity is feasible.

Advances in Microelectronics for Implantable Medical Devices

Implantable medical devices provide therapy to treat numerous health conditions as well as monitoring and diagnosis. Over the years, the development of these devices has seen remarkable progress thanks to tremendous advances in microelectronics, electrode technology, packaging and signal processing techniques. Many of today’s implantable devices use wireless technology to supply power and provide communication. There are many challenges when creating an implantable device. Issues such as reliable and fast bidirectional data communication, efficient power delivery to the implantable circuits, low noise and low power for the recording part of the system, and delivery of safe stimulation to avoid tissue and electrode damage are some of the challenges faced by the microelectronics circuit designer. This paper provides a review of advances in microelectronics over the last decade or so for implantable medical devices and systems. The focus is on neural recording and stimulation circuits suitable for fabrication in modern silicon process technologies and biotelemetry methods for power and data transfer, with particular emphasis on methods employing radio frequency inductive coupling. The paper concludes by highlighting some of the issues that will drive future research in the field.

Development of an ultra low noise, miniature signal conditioning device for vestibular evoked response recordings

BACKGROUND

Inner ear evoked potentials are small amplitude (<1 μVpk) signals that require a low noise signal acquisition protocol for successful extraction; an existing such technique is Electrocochleography (ECOG). A novel variant of ECOG called Electrovestibulography (EVestG) is currently investigated by our group, which captures vestibular responses to a whole body tilt. The objective is to design and implement a bio-signal amplifier optimized for ECOG and EVestG, which will be superior in noise performance compared to low noise, general purpose devices available commercially.

METHOD

A high gain configuration is required (>85 dB) for such small signal recordings; thus, background power line interference (PLI) can have adverse effects. Active electrode shielding and driven-right-leg circuitry optimized for EVestG/ECOG recordings were investigated for PLI suppression. A parallel pre-amplifier design approach was investigated to realize low voltage, and current noise figures for the bio-signal amplifier.

RESULTS

In comparison to the currently used device, PLI is significantly suppressed by the designed prototype (by >20 dB in specific test scenarios), and the prototype amplifier generated noise was measured to be 4.8 nV/Hz @ 1 kHz (0.45 μVRMS with bandwidth 10 Hz-10 kHz), which is lower than the currently used device generated noise of 7.8 nV/Hz @ 1 kHz (0.76 μVRMS). A low noise (<1 nV/Hz) radio frequency interference filter was realized to minimize noise contribution from the pre-amplifier, while maintaining the required bandwidth in high impedance measurements. Validation of the prototype device was conducted for actual ECOG recordings on humans that showed an increase (p < 0.05) of ~5 dB in Signal-to-Noise ratio (SNR), and for EVestG recordings using a synthetic ear model that showed a ~4% improvement (p < 0.01) over the currently used amplifier.

CONCLUSION

This paper presents the design and evaluation of an ultra-low noise and miniaturized bio-signal amplifier tailored for EVestG and ECOG. The increase in SNR for the implemented amplifier will reduce variability associated with bio-features extracted from such recordings; hence sensitivity and specificity measures associated with disease classification are expected to increase. Furthermore, immunity to PLI has enabled EVestG and ECOG recordings to be carried out in a non-shielded clinical environment.

A low-power current-reuse dual-band analog front-end for multi-channel neural signal recording

Thoroughly studying the brain activity of freely moving subjects requires miniature data acquisition systems to measure and wirelessly transmit neural signals in real time. In this application, it is mandatory to simultaneously record the bioelectrical activity of a large number of neurons to gain a better knowledge of brain functions. However, due to limitations in transferring the entire raw data to a remote base station, employing dedicated data reduction techniques to extract the relevant part of neural signals is critical to decrease the amount of data to transfer. In this work, we present a new dual-band neural amplifier to separate the neuronal spike signals (SPK) and the local field potential (LFP) simultaneously in the analog domain, immediately after the pre-amplification stage. By separating these two bands right after the pre-amplification stage, it is possible to process LFP and SPK separately. As a result, the required dynamic range of the entire channel, which is determined by the signal-to-noise ratio of the SPK signal of larger bandwidth, can be relaxed. In this design, a new current-reuse low-power low-noise amplifier and a new dual-band filter that separates SPK and LFP while saving capacitors and pseudo resistors. A four-channel dual-band (SPK, LFP) analog front-end capable of simultaneously separating SPK and LFP is implemented in a TSMC 0.18 μm technology. Simulation results present a total power consumption per channel of 3.1 μw for an input referred noise of 3.28 μV and a NEF for 2.07. The cutoff frequency of the LFP band is fc=280 Hz, and fL=725 Hz and fL=11.2 KHz for SPK, with 36 dB gain for LFP band 46 dB gain for SPK band.

A 0.09 μW low power front-end biopotential amplifier for biosignal recording

This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm². With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09μW, respectively.

A 4 μW/Ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-D neural microsystems

We report an analog front-end prototype designed in 0.25 μm CMOS process for hybrid integration into 3-D neural recording microsystems. For scaling towards massive parallel neural recording, the prototype has investigated some critical circuit challenges in power, area, interface, and modularity. We achieved extremely low power consumption of 4 μW/channel, optimized energy efficiency using moderate inversion in low-noise amplifiers (K of 5.98 × 10⁸ or NEF of 2.9), and minimized asynchronous interface (only 2 per 16 channels) for command and data capturing. We also implemented adaptable operations including programmable-gain amplification, power-scalable sampling (up to 50 kS/s/channel), wide configuration range (9-bit) for programmable gain and bandwidth, and 5-bit site selection capability (selecting 16 out of 128 sites). The implemented front-end module has achieved a reduction in noise-energy-area product by a factor of 5-25 times as compared to the state-of-the-art analog front-end approaches reported to date.

A low-power programmable neural spike detection channel with embedded calibration and data compression

This paper reports a programmable 400 μm pitch neural spike recording channel, fabricated in a 130 nm standard CMOS technology, which implements amplification, filtering, digitization, analog spike detection plus feature extraction, and self-calibration functionalities. It can operate in two different output modes: 1) signal tracking, in which the neural signal is sampled and transmitted as raw data; and 2) feature extraction, in which the spikes of the neural signal are detected and encoded by piece-wise linear curves. Additionally, the channel offers a foreground calibration procedure in which the amplification gain and the passband of the embedded filter can be self-adjusted. The amplification stage obtains a noise efficiency factor of 2.16 and an input referred noise of 2.84 μVrms over a nominal bandwidth of 167 Hz-6.9 kHz. The channel includes a reconfigurable 8-bit analog-to-digital converter combined with a 3-bit controlled programmable gain amplifier for adjusting the input signal to the full scale range of the converter. This combined block achieves an overall energy consumption per conversion of 102 fJ at 90 kS/s. The energy consumed by the circuit elements which are strictly related to the digitization process is 14.12 fJ at the same conversion rate. The complete channel consumes 2.8 μW at 1.2 V voltage supply when operated in the signal tracking mode, and 3.1 μW when the feature extraction mode is enabled.

A novel low-power-implantable epileptic seizure-onset detector

A novel implantable low-power integrated circuit is proposed for real-time epileptic seizure detection. The presented chip is part of an epilepsy prosthesis device that triggers focal treatment to disrupt seizure progression. The proposed chip integrates a front-end preamplifier, voltage-level detectors, digital demodulators, and a high-frequency detector. The preamplifier uses a new chopper stabilizer topology that reduces instrumentation low-frequency and ripple noises by modulating the signal in the analog domain and demodulating it in the digital domain. Moreover, each voltage-level detector consists of an ultra-low-power comparator with an adjustable threshold voltage. The digitally integrated high-frequency detector is tunable to recognize the high-frequency activities for the unique detection of seizure patterns specific to each patient. The digitally controlled circuits perform accurate seizure detection. A mathematical model of the proposed seizure detection algorithm was validated in Matlab and circuits were implemented in a 2 mm(2) chip using the CMOS 0.18- μm process. The proposed detector was tested by using intracerebral electroencephalography (icEEG) recordings from seven patients with drug-resistant epilepsy. The seizure signals were assessed by the proposed detector and the average seizure detection delay was 13.5 s, well before the onset of clinical manifestations. The measured total power consumption of the detector is 51 μW.

Energy efficient low-noise neural recording amplifier with enhanced noise efficiency factor

This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology, which utilizes a differential pair input stage. The proposed architecture, which is referred to as a partial operational transconductance amplifier sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of mismatch on crosstalk between channels and the tradeoff between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a -3-dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at 3.5 μVrms and the power consumption is 7.92 μW from a 1.8-V supply, which corresponds to NEF = 3.35. The worst-case crosstalk and common-mode rejection ratio within the desired bandwidth are - 43.5 dB and 70.1 dB, respectively, and the active silicon area of each amplifier is 256 μm × 256 μm in 0.18-μm complementary metal-oxide semiconductor technology.

Recent advances in neural recording microsystems

The accelerating pace of research in neuroscience has created a considerable demand for neural interfacing microsystems capable of monitoring the activity of large groups of neurons. These emerging tools have revealed a tremendous potential for the advancement of knowledge in brain research and for the development of useful clinical applications. They can extract the relevant control signals directly from the brain enabling individuals with severe disabilities to communicate their intentions to other devices, like computers or various prostheses. Such microsystems are self-contained devices composed of a neural probe attached with an integrated circuit for extracting neural signals from multiple channels, and transferring the data outside the body. The greatest challenge facing development of such emerging devices into viable clinical systems involves addressing their small form factor and low-power consumption constraints, while providing superior resolution. In this paper, we survey the recent progress in the design and the implementation of multi-channel neural recording Microsystems, with particular emphasis on the design of recording and telemetry electronics. An overview of the numerous neural signal modalities is given and the existing microsystem topologies are covered. We present energy-efficient sensory circuits to retrieve weak signals from neural probes and we compare them. We cover data management and smart power scheduling approaches, and we review advances in low-power telemetry. Finally, we conclude by summarizing the remaining challenges and by highlighting the emerging trends in the field.

Epileptic seizure onset detection prior to clinical manifestation

In this paper, we present the design of an epilepticseizure detector. This circuit is part of an implantable device used to continuously record intracerebral electroencephalographic signals through subdural and depth electrodes. The implemented seizure detector is based on a detection algorithm validated in Matlab tools and the circuits were implemented using CMOS 0.18-microm process. The proposed system was tested using intracerebral EEG recordings from two patients with drug-resistant epilepsy. Four seizures were assessed by the proposed CMOS building blocks and the required delays to detect these seizures were 3, 8, 11, and 11 sec, respectively after electric onset. The simulated total power consumption of the detector was 6.71 microW. Together, these preliminary results indicate the possibility of building implantable ultra-low power seizure-detection devices.

The 128-channel fully differential digital integrated neural recording and stimulation interface

We present a fully differential 128-channel integrated neural interface. It consists of an array of 8 X 16 low-power low-noise signal-recording and generation circuits for electrical neural activity monitoring and stimulation, respectively. The recording channel has two stages of signal amplification and conditioning with and a fully differential 8-b column-parallel successive approximation (SAR) analog-to-digital converter (ADC). The total measured power consumption of each recording channel, including the SAR ADC, is 15.5 ¿W. The measured input-referred noise is 6.08 ¿ Vrms over a 5-kHz bandwidth, resulting in a noise efficiency factor of 5.6. The stimulation channel performs monophasic or biphasic voltage-mode stimulation, with a maximum stimulation current of 5 mA and a quiescent power dissipation of 51.5 ¿W. The design is implemented in 0.35-¿m complementary metal-oxide semiconductor technology with the channel pitch of 200 ¿m for a total die size of 3.4 mm × 2.5 mm and a total power consumption of 9.33 mW. The neural interface was validated in in vitro recording of a low-Mg(2+)/high-K(+) epileptic seizure model in an intact hippocampus of a mouse.

Analog integrated circuits design for processing physiological signals

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

A cell-electrode interface noise model for high-density microelectrode arrays

A cell-electrode interface noise model is developed which is dedicated to enable the co-simulation of the cell-electrode electrical characteristics, along with the electronics of novel CMOS-based MEA. The electrode noise is investigated for Pt and Pt black electrodes. It is shown that the electrode noise can be the dominant noise source in the full system. Moreover, Pt black electrodes benefit from up to 5 microV(rms) decrease of the electrode output noise, for small electrodes. Furthermore, the cell-electrode interface noise spectral density is shown to be 10 dB to 20 dB larger at 1 kHz when a cell is lying on top of the electrode. This increase depends on the neural cell adhesion on the MEA surface.

A mixed-signal multichip neural recording interface with bandwidth reduction

We present a multichip structure assembled with a medical-grade stainless-steel microelectrode array intended for neural recordings from multiple channels. The design features a mixed-signal integrated circuit (IC) that handles conditioning, digitization, and time-division multiplexing of neural signals, and a digital IC that provides control, bandwidth reduction, and data communications for telemetry toward a remote host. Bandwidth reduction is achieved through action potential detection and complete capture of waveforms by means of onchip data buffering. The adopted architecture uses high parallelism and low-power building blocks for safety and long-term implantability. Both ICs are fabricated in a CMOS 0.18-mum process and are subsequently mounted on the base of the microelectrode array. The chips are stacked according to a vertical integration approach for better compactness. The presented device integrates 16 channels, and is scalable to hundreds of recording channels. Its performance was validated on a testbench with synthetic neural signals. The proposed interface presents a power consumption of 138 muW per channel, a size of 2.30 mm(2), and achieves a bandwidth reduction factor of up to 48 with typical recordings.

A 1microW 85nV/ radicalHz pseudo open-loop preamplifier with programmable band-pass filter for neural interface system

We report an energy efficient pseudo open-loop amplifier with programmable band-pass filter developed for neural interface systems. The proposed amplifier consumes 400nA at 2.5V power supply. The measured thermal noise level is 85nV/ radicalHz and input-referred noise is 1.69microV(rms) from 0.3Hz to 1 kHz. The amplifier has a noise efficiency factor of 2.43, the lowest in the differential topologies reported up to date to our knowledge. By programming the switched-capacitor frequency and bias current, we could control the bandwidth of the preamplifier from 138 mHz to 2.2 kHz to meet various application requirements. The entire preamplifier including band-pass filters has been realized in a small area of 0.043mm(2) using a 0.25microm CMOS technology.