Design and Characteristics of a Multichannel Front-End ASIC Using Current-Mode CSA for Small-Animal PET Imaging

Radiation Detector Front-End Readout Chip with Nonbinary Successive Approximation Register Analog-to-Digital Converter for Wearable Healthcare Monitoring Applications

A 16-channel front-end readout chip for a radiation detector is designed for portable or wearable healthcare monitoring applications. The proposed chip reads the signal of the radiation detector and converts it into digital serial-out data by using a nonbinary successive approximation register (SAR) analog-to-digital converter (ADC) that has a 1-MS/s sampling rate and 10-b resolution. The minimum-to-maximum differential and integral nonlinearity are measured as -0.32 to 0.33 and -0.43 to 0.37 least significant bits, respectively. The signal-to-noise-and-distortion ratio and effective number of bits are 57.41 dB and 9.24 bits, respectively, for an input frequency of 500 kHz and a sampling rate of 1 MS/s. The SAR ADC has a 38.9-fJ/conversion step figure of merit at the sampling rate of 1 MS/s. The proposed chip can read input signals with peak currents ranging from 20 to 750 μA and convert the analog signal into a 10-bit serial-output digital signal. The input dynamic range is 2-75 pC. The resolution of the peak current is 208.3 nA. The chip, which has an area of 1.444 mm × 10.568 mm, is implemented using CMOS 0.18-μm 1P6M technology, and the power consumption of each channel is 19 mW. This design is suitable for wearable devices, especially biomedical devices.

Silicon photomultiplier signal readout and multiplexing techniques for positron emission tomography: a review

In recent years, silicon photomultiplier (SiPM) is replacing the photomultiplier tube (PMT) in positron emission tomography (PET) systems due to its superior properties, such as fast single-photon timing response, small gap between adjacent photosensitive pixels in the array, and insensitivity to magnetic fields. One of the technical challenges when developing SiPM-based PET systems or other position-sensitive radiation detectors is the large number of output channels coming from the SiPM array. Therefore, various signal multiplexing methods have been proposed to reduce the number of output channels and the load on the subsequent data acquisition (DAQ) system. However, the large PN-junction capacitance and quenching resistance of the SiPM yield undesirable resistance-capacitance delay when multiple SiPMs are combined, which subsequently causes the accumulation of dark counts and signal fluctuation of SiPMs. Therefore, without proper SiPM signal handling and processing, the SiPMs may yield worse timing characteristics than the PMTs. This article reviews the evolution of signal readout and multiplexing methods for the SiPM. In this review, we focus primarily on analog electronics for SiPM signal multiplexing, which allows for the reduction of DAQ channels required for the SiPM-based position-sensitive detectors used in PET and other radiation detector systems. Although the applications of most technologies described in the article are not limited to PET systems, the review highlights efforts to improve the physical performance (e.g. spatial, energy, and timing resolutions) of PET detectors and systems.

A high resolution time-to-digital-convertor based on a carry-chain and DSP48E1 adders in a 28-nm field-programmable-gate-array

A field-programmable-gate-array (FPGA) based time-to-digital-converter (TDC), which combines different types of delay chains in a single time measurement channel, is reported in this paper. A new TDC architecture is developed, and both a carry-chain and the DSP48E1 adders, which are integrated inside the FPGA chip, are employed to achieve high resolution time tagging. A single channel TDC has a 3.3 ps averaged bin size, a 5.4 ps single-shot precision, and a maximum sampling rate of 250 MSa/s. The differential-non-linearity of the single TDC channel is -3.3 ps/+24.1 ps, and the integral-non-linearity is within -10.4 ps/+68.6 ps. The TDC performance can be improved by using four TDC channels to measure one input signal, and a 3.4 ps single-shot precision can be obtained. Due to the implementation of the delicated TDC structure, only a small amount of digital resources is required to achieve the picosecond time measurement resolution. Therefore, the reported TDC architecture is suitable for multi-channel applications that require high time resolution measurements of multiple input signals.

A Readout IC Using Two-Step Fastest Signal Identification for Compact Data Acquisition of PET Systems

A readout integrated circuit (ROIC) using two-step fastest signal identification (FSI) is proposed to reduce the number of input channels of a data acquisition (DAQ) block with a high-channel reduction ratio. The two-step FSI enables the proposed ROIC to filter out useless input signals that arise from scattering and electrical noise without using complex and bulky circuits. In addition, an asynchronous fastest signal identifier and a self-trimmed comparator are proposed to identify the fastest signal without using a high-frequency clock and to reduce misidentification, respectively. The channel reduction ratio of the proposed ROIC is 16:1 and can be extended to 16 × N:1 using N ROICs. To verify the performance of the two-step FSI, the proposed ROIC was implemented into a gamma photon detector module using a Geiger-mode avalanche photodiode with a lutetium-yttrium oxyorthosilicate array. The measured minimum detectable time is 1 ns. The difference of the measured energy and timing resolution between with and without the two-step FSI are 0.8% and 0.2 ns, respectively, which are negligibly small. These measurement results show that the proposed ROIC using the two-step FSI reduces the number of input channels of the DAQ block without sacrificing the performance of the positron emission tomography (PET) systems.

A Low-Power Gateable Vernier Ring Oscillator Time-to-Digital Converter for Biomedical Imaging Applications

In this paper, a high resolution, high precision and ultra-low power consumption time-to-digital converter (TDC) is presented. The proposed TDC is based on the gateable Vernier ring oscillator architecture. Fine resolution is achieved through two ring oscillators arranged in the Vernier configuration. This TDC employs a single-transition end-of-conversion detection circuit and turns off the ring oscillators whenever the conversion is completed to reduce power consumption. The prototype chip is fabricated in a standard 130 nm digital CMOS process and its area is only 0.03 mm(2). Using a 1.2 V supply, the TDC achieves a resolution of 7.3 ps, a single-shot precision of 1.0LSB, and an average power consumption of 1.2 mW. A root-mean-square integral nonlinearity (INL) of 1.2 LSB is obtained with the help of an INL look-up-table calibration. Compared to previously reported ring-oscillator based TDCs, the proposed design achieves the lowest power consumption to date.

A wireless capsule system with ASIC for monitoring the physiological signals of the human gastrointestinal tract

This paper presents the design of a wireless capsule system for monitoring the physiological signals of the human gastrointestinal (GI) tract. The primary components of the system include a wireless capsule, a portable data recorder, and a workstation. Temperature, pH, and pressure sensors; an RF transceiver; a controlling and processing application specific integrated circuit (ASIC); and batteries were applied in a wireless capsule. Decreasing capsule size, improving sensor precision, and reducing power needs were the primary challenges; these were resolved by employing micro sensors, optimized architecture, and an ASIC design that include power management, clock management, a programmable gain amplifier (PGA), an A/D converter (ADC), and a serial peripheral interface (SPI) communication unit. The ASIC has been fabricated in 0.18- μm CMOS technology with a die area of 5.0 mm × 5.0 mm. The wireless capsule integrating the ASIC controller measures Φ 11 mm × 26 mm. A data recorder and a workstation were developed, and 20 cases of human experiments were conducted in hospitals. Preprocessing in the workstation can significantly improve the quality of the data, and 76 original features were determined by mathematical statistics. Based on the 13 optimal features achieved in the evaluation of the features, the clustering algorithm can identify the patients who lack GI motility with a recognition rate reaching 83.3%.

A highly linear fully integrated powerline filter for biopotential acquisition systems

Powerline interference is one of the most dominant problems in detection and processing of biopotential signals. This work presents a new fully integrated notch filter exhibiting high linearity and low power consumption. High filter linearity is preserved utilizing active-RC approach while IC implementation is achieved through replacing passive resistors by R-2R ladders achieving area saving of approximately 120 times. The filter design is optimized for low power operation using an efficient circuit topology and an ultra-low power operational amplifier. Fully differential implementation of the proposed filter shows notch depth of 43 dB (78 dB for 4th-order) with THD of better than -70 dB while consuming about 150 nW from 1.5 V supply.

Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems

Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs).

Impact of Analog IC Impairments in SiPM Interface Electronics

The recent realization of Silicon Photomultiplier (SiPM) devices as solid-state detectors for Positron Emission Tomography holds the promise of improving image resolution, integrating a significant portion of the interface electronics, and potentially lowering the power consumption. Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing and is currently working on taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. To date, relatively little modeling has been done to understand the impact of analog non-idealities associated with the front-end electronics, on SiPM-based PET systems. This paper focuses on various analog impairments associated with PET scanner readout electronics. Matlab was used as a simulation platform to model the noise, linearity and signal bandwidth of the frontend electronics with the measured SiPM pulses as the input.