A 4 μW/Ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-D neural microsystems

Design of a low-noise low-voltage amplifier for improved neural signal recording

Design of amplifier circuits with low-noise operable at low-power to be used, especially for implantable neural interfaces, remains a huge challenge. This research paper presents the design of a low-noise low-voltage neural recording amplifier suitable for amplifying local field potentials and extracellular action potentials so as to meet the end requirement of an implantable neuro-medical system. Critical performance parameters of the smaller circuit blocks of the complete neural amplifier architecture have been found with the help of detailed mathematical analysis and then verified by the simulations conducted using 0.18 µm 4M1P foundry Semi-conductor Laboratory N-well process. The neural amplifier design proposed in this paper passes neural signal of interest with a mid-band gain of 49.9 dB over a bandwidth of 5.3 Hz-8.6 kHz, draws only 11.5 µW of power from ±0.9 V supply voltage, and exhibits an input-referred noise of 2.6 µV_rms with a noise efficiency factor of 2.27. The area consumed by the proposed neural amplifier architecture is 0.192 mm². The complete circuit design carried out in this paper should prove to be useful in equipment for the diagnosis of neurological disorders.

A Reconfigurable Differential-to-Single-Ended Autonomous Current Adaptation Buffer Amplifier Suitable for Biomedical Applications

A reconfigurable differential-to-single-ended autonomous current adaptation buffer amplifier (ACABA) is proposed. The ACABA, based on floating-gate technologies, is a capacitive circuit, of which output DC level and bandwidth can be adjusted by programming charges on floating nodes. The gain is variable by switching different amounts of capacitors without altering the output DC level. Without extra sensing and control circuitries, the current consumption of the proposed ACABA increases spontaneously when the input signal is fast or large, achieving a high slew rate. The supply current dwindles back to the low quiescent level autonomously when the output voltage reaches equilibrium. Therefore, the proposed ACABA is power-efficient and suitable for processing physiological signals. A prototype ACABA has been designed and fabricated in a [Formula: see text] CMOS process occupying an area of [Formula: see text]. When loaded by a [Formula: see text] capacitor, it consumes [Formula: see text] to achieve a unity-gain bandwidth of [Formula: see text] with a measured IIP2 value of [Formula: see text] and a slew rate of [Formula: see text].

Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes

Highly integrated neural sensing microsystems are crucial to capture accurate signals for brain function investigations. In this paper, a 256-channel neural sensing microsystem with a sensing area of 5 × 5 mm ² is presented based on 2.5-D through-silicon-via (TSV) integration. This microsystem composes of dissolvable μ-needles, TSV-embedded μ-probes, 256-channel neural amplifiers, 11-bit area-power-efficient successive approximation register analog-to-digital converters, and serializers. This microsystem can detect 256 electrocorticography and local field potential signals within a small area of 5 mm × 5 mm. The neural amplifier realizes 57.8 dB gain with only 9.8 μW per channel. The overall power of this microsystem is only 3.79 mW for 256-channel neural sensing. A smaller microsystem with dimension of 6 mm × 4 mm has been also implanted into rat brain for somatosensory evoked potentials (SSEPs) recording by using contralateral and ipsilateral electrical stimuli with intensity from 0.2 to 1.0 mA, and successfully observed different SSEPs from left somatosensory cortex of a rat.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

A PWM Buck Converter With Load-Adaptive Power Transistor Scaling Scheme Using Analog-Digital Hybrid Control for High Energy Efficiency in Implantable Biomedical Systems

We report a pulse width modulation (PWM) buck converter that is able to achieve a power conversion efficiency (PCE) of > 80% in light loads 100 μA) for implantable biomedical systems. In order to achieve a high PCE for the given light loads, the buck converter adaptively reconfigures the size of power PMOS and NMOS transistors and their gate drivers in accordance with load currents, while operating at a fixed frequency of 1 MHz. The buck converter employs the analog-digital hybrid control scheme for coarse/fine adjustment of power transistors. The coarse digital control generates an approximate duty cycle necessary for driving a given load and selects an appropriate width of power transistors to minimize redundant power dissipation. The fine analog control provides the final tuning of the duty cycle to compensate for the error from the coarse digital control. The mode switching between the analog and digital controls is accomplished by a mode arbiter which estimates the average of duty cycles for the given load condition from limit cycle oscillations (LCO) induced by coarse adjustment. The fabricated buck converter achieved a peak efficiency of 86.3% at 1.4 mA and > 80% efficiency for a wide range of load conditions from 45 μA to 4.1 mA, while generating 1 V output from 2.5-3.3 V supply. The converter occupies 0.375 mm(2) in 0.18 μm CMOS processes and requires two external components: 1.2 μF capacitor and 6.8 μH inductor.

Tools for probing local circuits: high-density silicon probes combined with optogenetics

To understand how function arises from the interactions between neurons, it is necessary to use methods that allow the monitoring of brain activity at the single-neuron, single-spike level and the targeted manipulation of the diverse neuron types selectively in a closed-loop manner. Large-scale recordings of neuronal spiking combined with optogenetic perturbation of identified individual neurons has emerged as a suitable method for such tasks in behaving animals. To fully exploit the potential power of these methods, multiple steps of technical innovation are needed. We highlight the current state of the art in electrophysiological recording methods, combined with optogenetics, and discuss directions for progress. In addition, we point to areas where rapid development is in progress and discuss topics where near-term improvements are possible and needed.

2.5D heterogeneously integrated microsystem for high-density neural sensing applications

Heterogeneously integrated and miniaturized neural sensing microsystems are crucial for brain function investigation. In this paper, a 2.5D heterogeneously integrated bio-sensing microsystem with μ-probes and embedded through-silicon-via (TSVs) is presented for high-density neural sensing applications. This microsystem is composed of μ-probes with embedded TSVs, 4 dies and a silicon interposer. For capturing 16-channel neural signals, a 24 × 24 μ-probe array with embedded TSVs is fabricated on a 5×5 mm(2) chip and bonded on the back side of the interposer. Thus, each channel contains 6 × 6 μ -probes with embedded TSVs. Additionally, the 4 dies are bonded on the front side of the interposer and designed for biopotential acquisition, feature extraction and classification via low-power analog front-end (AFE) circuits, area-power-efficient analog-to-digital converters (ADCs), configurable discrete wavelet transforms (DWTs), filters, and a MCU. An on-interposer bus ( μ-SPI) is designed for transferring data on the interposer. Finally, the successful in-vivo test demonstrated the proposed 2.5D heterogeneously integrated bio-sensing microsystem. The overall power of this microsystem is only 676.3 μW for 16-channel neural sensing.

A 0.45 V 100-channel neural-recording IC with sub- μW/channel consumption in 0.18 μm CMOS

Neural prosthetics and personal healthcare have increasing need of high channel density low noise low power neural sensor interfaces. The input referred noise and quantization resolution are two essential factors which prevent conventional neural sensor interfaces from simultaneously achieving a good noise efficiency factor and low power consumption. In this paper, a neural recording architecture with dynamic range folding and current reuse techniques is proposed and dedicated to solving the noise and dynamic range trade-off under low voltage low power operation. Measured results from the silicon prototype show that the proposed design achieves 3.2 μVrms input referred noise and 8.27 effective number of bits at only 0.45 V supply and 0.94 μW/channel power consumption.

Design and implementation of a wireless in-ovo EEG/EMG recorder

The developmental origins of sleep and brain activity rhythms in higher vertebrate animals (birds and mammals) are currently unknown. In order to create an experimental system in which these could be better elucidated, we designed, built and tested a system for recording EEG and EMG signals in-ovo from chicken embryos incubated for 16-21 days. This system can remain attached to the individual subject through the process of hatching and continue to be worn post-natally. Electrode wires surgically implanted on the head of the embryo are connected to a battery-operated ultraportable transmitter which can either be attached to the eggshell or worn on the back. The transmitter processes up to 6 channels of data with a maximum sampling frequency of 500 Hz and a resolution of 12 bits. The radio link uses a carrier frequency of 4 MHz, and has a maximum transfer rate of 500 kbit/s; receiving antennas compatible with both in-egg recordings and post-natal recordings from freely-moving birds were produced. A receiver connected with one USB port of a PC transmits the data for digital storage. This system is based on discrete, off-the-shelf components, can provide a few days of continuous operation with a single lithium coin battery, and has a noise floor level of 0.35 μV. The transmitter dimensions are 16 × 13 × 1.5 mm and the weight without the battery is 0.7 g. The microprocessor allows flexible operation modes not usually made available in other small multichannel acquisition systems implemented by means of ad hoc mixed signal chips.

A 4 μW/Ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-D neural microsystems

We report an analog front-end prototype designed in 0.25 μm CMOS process for hybrid integration into 3-D neural recording microsystems. For scaling towards massive parallel neural recording, the prototype has investigated some critical circuit challenges in power, area, interface, and modularity. We achieved extremely low power consumption of 4 μW/channel, optimized energy efficiency using moderate inversion in low-noise amplifiers (K of 5.98 × 10⁸ or NEF of 2.9), and minimized asynchronous interface (only 2 per 16 channels) for command and data capturing. We also implemented adaptable operations including programmable-gain amplification, power-scalable sampling (up to 50 kS/s/channel), wide configuration range (9-bit) for programmable gain and bandwidth, and 5-bit site selection capability (selecting 16 out of 128 sites). The implemented front-end module has achieved a reduction in noise-energy-area product by a factor of 5-25 times as compared to the state-of-the-art analog front-end approaches reported to date.