Data compression in brain-machine/computer interfaces based on the Walsh-Hadamard transform

A hardware-efficient on-implant spike compression processor based on VQ-DAE for brain-implantable microsystems

High-density implantable neural recording microsystems deal with a huge amount of data. Since the wireless transmission of the raw recorded data leads to excessive bandwidth requirements, spike compression approaches have become vital to such systems. The compression processor is designed to be implemented on the implant and so to avoid any tissue damage, the hardware cost of the processor is of great importance. The vector quantization (VQ) algorithm has proven to be effective in compression applications and spike compression systems as well. In this paper, benefiting from the capabilities of the denoising autoencoders (DAE), we propose a solution to enhance the compression performance of the VQ-based approach in terms of both reconstruction accuracy and hardware efficiency. Moreover, we develop a hardware-efficient multi-channel architecture for the proposed VQ-DAE processor. The processor has been implemented in a 180-nm CMOS technology and the validation and verification processes confirm that it provides satisfactory results. It achieves an average signal-to-noise-distortion (SNDR) of 14.51 at a spike compression ratio (SCR) of 30. Operated at a clock frequency of 192 kHz and a supply voltage of 1.8 V, the circuit consumes a power of 4.88 μ W and a silicon area of 0.14 mm2 per channel.

68-channel neural signal processing system-on-chip with integrated feature extraction, compression, and hardware accelerators for neuroprosthetics in 22 nm FDSOI

Introduction

Multi-channel electrophysiology systems for recording of neuronal activity face significant data throughput limitations, hampering real-time, data-informed experiments. These limitations impact both experimental neurobiology research and next-generation neuroprosthetics.

Methods

We present a novel solution that leverages the high integration density of 22nm fully-depleted silicon-on-insulator technology to address these challenges. The proposed highly integrated programmable System-on-Chip (SoC) comprises 68-channel 0.41 μW/Ch recording frontends, spike detectors, 16-channel 0.87-4.39 μW/Ch action potentials and 8-channel 0.32 μW/Ch local field potential codecs, as well as a multiply-accumulate-assisted power-efficient processor operating at 25 MHz (5.19 μW/MHz). The system supports on-chip training processes for compression, training, and inference for neural spike sorting. The spike sorting achieves an average accuracy of 91.48 or 94.12% depending on the utilized features. The proposed programmable SoC is optimized for reduced area (9 mm2) and power. On-chip processing and compression capabilities free up the data bottlenecks in data transmission (up to 91% space saving ratio), and moreover enable a fully autonomous yet flexible processor-driven operation.

Discussion

Combined, these design considerations overcome data-bottlenecks by allowing on-chip feature extraction and subsequent compression.

Bioelectronic Sensor Nodes for the Internet of Bodies

Energy-efficient sensing with physically secure communication for biosensors on, around, and within the human body is a major area of research for the development of low-cost health care devices, enabling continuous monitoring and/or secure perpetual operation. When used as a network of nodes, these devices form the Internet of Bodies, which poses challenges including stringent resource constraints, simultaneous sensing and communication, and security vulnerabilities. Another major challenge is to find an efficient on-body energy-harvesting method to support the sensing, communication, and security submodules. Due to limitations in the amount of energy harvested, we require a reduction in energy consumed per unit information, making the use of in-sensor analytics and processing imperative. In this article, we review the challenges and opportunities of low-power sensing, processing, and communication with possible powering modalities for future biosensor nodes. Specifically, we analyze, compare, and contrast (a) different sensing mechanisms such as voltage/current domain versus time domain, (b) low-power, secure communication modalities including wireless techniques and human body communication, and (c) different powering techniques for wearable devices and implants.

Intertwined-pulse modulation for compressive data telemetry

This paper presents a novel approach for anisochronous pulse-based modulation. In the proposed approach, referred to as the intertwined-pulse modulation (IPM), every pair of consecutive symbols overlap in time. This allows for shortening the time allocated for the transmission of the symbols, hence achieving temporal compaction while the data goes through the line encoding step in a digital communication system. The IPM is also uniquely superior to other existing anisochronous pulse-based modulation schemes in the fact that it exhibits robust symbol error rate against unwanted variations in both rise/fall times of the pulses in the modulated waveform, and in the threshold level used for data detection on the receiver side. An experimental setup was developed to implement an IPM encoder using standard digital hardware, and an IPM decoder as a part of the receiver system in software. According to the experimental results (supported by simulation results and theoretical studies), for the data mean value of mid-full-scale range, the proposed IPM scheme exhibits a time-domain compaction rate of up to 209.2%.

A Vector Quantization-Based Spike Compression Approach Dedicated to Multichannel Neural Recording Microsystems

Implantable high-density multichannel neural recording microsystems provide simultaneous recording of brain activities. Wireless transmission of the entire recorded data causes high bandwidth usage, which is not tolerable for implantable applications. As a result, a hardware-friendly compression module is required to reduce the amount of data before it is transmitted. This paper presents a novel compression approach that utilizes a spike extractor and a vector quantization (VQ)-based spike compressor. In this approach, extracted spikes are vector quantized using an unsupervised learning process providing a high spike compression ratio (CR) of 10-80. A combination of extracting and compressing neural spikes results in a significant data reduction as well as preserving the spike waveshapes. The compression performance of the proposed approach was evaluated under variant conditions. We also developed new architectures such that the hardware blocks of our approach can be implemented more efficiently. The compression module was implemented in a 180-nm standard CMOS process achieving a SNDR of 14.49[Formula: see text]dB and a classification accuracy (CA) of 99.62% at a CR of 20, while consuming 4[Formula: see text][Formula: see text]W power and 0.16[Formula: see text]mm² chip area per channel.

Spatial Redundancy Reduction in Multi-Channel Implantable Neural Recording Microsystems

This paper introduces a lossless approach for data reduction in multi-channel neural recording microsystems. The proposed approach benefits from eliminating the redundancy that exists in the signals recorded from the same space in the brain, e.g., local field potentials in intra-cortical recording from neighboring recording sites. In this approach, a single baseline component is extracted from the original neural signals, which is treated as the component all the channels share in common. What remains is a set of channel-specific difference components, which are much smaller in word length compared to the sample size of the original neural signals. To make the proposed approach more efficient in data reduction, length of the difference component words is adaptively determined according to their instantaneous amplitudes. This approach is low in both computational and hardware complexity, which introduces it as an attractive suggestion for high-density neural recording brain implants. Applied on multi-channel neural signals intra-cortically recorded using 16 multi-electrode array, the data is reduced by around 48%. Designed in TSMC 130-nm standard CMOS technology, hardware implementation of this technique for 16 parallel channels occupies a silicon area of 0.06 mm², and dissipates 6.4 μW of power per channel when operates at V_DD=1.2V and 400 kHz.Clinical Relevance- This paper presents a lossless data reduction technique, dedicated to brain-implantable neural recording devices. Such devices are developed for clinical applications such as the treatment of epilepsy, neuro-prostheses, and brain-machine interfacing for therapeutic purposes.

Hardware and Power-Efficient Compression Technique Based on Discrete Tchebichef Transform for Neural Recording Microsystems

In this paper a new compression technique based on the discrete Tchebichef transform is presented. To comply with strict on-implant hardware implementation requirements, such as low power dissipation and small silicon area consumption, the discrete Tchebichef transform is modified and truncated. An algorithm is proposed to generate approximate transform matrices capable of truncation without suffering from destructive energy leakage among the coefficients. This is achieved by preserving orthogonality of the basis functions that convey majority portion of the signal energy. Based on the presented algorithm, a new truncated transformation matrix is proposed, which reduces the hardware complexity by up to 74% compared to that of the original transform. Hardware implementation of the proposed neural signal compression technique is prototyped using standard digital hardware. With pre-recorded neural signals as the input, compression rate of 26.15 is achieved while the root-mean-square of error is kept as low as 1.1%.Clinical Relevance- This paper proposes a technique for data compression in high-density neural recording brain implants, along with a power- and area-efficient hardware implementation. From among clinical applications of such implants one can point to neuro-prostheses, and brain-machine interfaces for therapeutic purposes.

A Streaming PCA VLSI Chip for Neural Data Compression

Neural recording system miniaturization and integration with low-power wireless technologies require compressing neural data before transmission. Feature extraction is a procedure to represent data in a low-dimensional space; its integration into a recording chip can be an efficient approach to compress neural data. In this paper, we propose a streaming principal component analysis algorithm and its microchip implementation to compress multichannel local field potential (LFP) and spike data. The circuits have been designed in a 65-nm CMOS technology and occupy a silicon area of 0.06 mm. Throughout the experiments, the chip compresses LFPs by 10 at the expense of as low as 1% reconstruction errors and 144-nW/channel power consumption; for spikes, the achieved compression ratio is 25 with 8% reconstruction errors and 3.05-W/channel power consumption. In addition, the algorithm and its hardware architecture can swiftly adapt to nonstationary spiking activities, which enables efficient hardware sharing among multiple channels to support a high-channel count recorder.

Efficient Hardware Implementation of Real-Time Low-Power Movement Intention Detector System Using FFT and Adaptive Wavelet Transform

The brain-computer interfacing (BCI), a platform to extract features and classify different motor movement tasks from noisy and highly correlated electroencephalogram signals, is limited mostly by the complex and power-hungry algorithms. Among different techniques recently devised to tackle this issue, real-time onset detection, due to its negligible delay and minimal power overhead, is the most efficient one. Here, we propose a novel algorithm that outperforms the state-of-the-art design by sixfold in terms of speed, without sacrificing the accuracy for a real-time, hand movement intention detection based on the adaptive wavelet transform with only 1 s detection delay and maximum sensitivity of 88% and selectivity of 78% (only 7% loss of sensitivity).

Active C4 Electrodes for Local Field Potential Recording Applications

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μV rms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented.

Strategies for high-performance resource-efficient compression of neural spike recordings

Brain-machine interfaces (BMIs) based on extracellular recordings with microelectrodes provide means of observing the activities of neurons that orchestrate fundamental brain function, and are therefore powerful tools for exploring the function of the brain. Due to physical restrictions and risks for post-surgical complications, wired BMIs are not suitable for long-term studies in freely behaving animals. Wireless BMIs ideally solve these problems, but they call for low-complexity techniques for data compression that ensure maximum utilization of the wireless link and energy resources, as well as minimum heat dissipation in the surrounding tissues. In this paper, we analyze the performances of various system architectures that involve spike detection, spike alignment and spike compression. Performance is analyzed in terms of spike reconstruction and spike sorting performance after wireless transmission of the compressed spike waveforms. Compression is performed with transform coding, using five different compression bases, one of which we pay special attention to. That basis is a fixed basis derived, by singular value decomposition, from a large assembly of experimentally obtained spike waveforms, and therefore represents a generic basis specially suitable for compressing spike waveforms. Our results show that a compression factor of 99.8%, compared to transmitting the raw acquired data, can be achieved using the fixed generic compression basis without compromising performance in spike reconstruction and spike sorting. Besides illustrating the relative performances of various system architectures and compression bases, our findings show that compression of spikes with a fixed generic compression basis derived from spike data provides better performance than compression with downsampling or the Haar basis, given that no optimization procedures are implemented for compression coefficients, and the performance is similar to that obtained when the optimal SVD based basis is used.