A Streaming PCA VLSI Chip for Neural Data Compression

A hardware-efficient on-implant spike compression processor based on VQ-DAE for brain-implantable microsystems

High-density implantable neural recording microsystems deal with a huge amount of data. Since the wireless transmission of the raw recorded data leads to excessive bandwidth requirements, spike compression approaches have become vital to such systems. The compression processor is designed to be implemented on the implant and so to avoid any tissue damage, the hardware cost of the processor is of great importance. The vector quantization (VQ) algorithm has proven to be effective in compression applications and spike compression systems as well. In this paper, benefiting from the capabilities of the denoising autoencoders (DAE), we propose a solution to enhance the compression performance of the VQ-based approach in terms of both reconstruction accuracy and hardware efficiency. Moreover, we develop a hardware-efficient multi-channel architecture for the proposed VQ-DAE processor. The processor has been implemented in a 180-nm CMOS technology and the validation and verification processes confirm that it provides satisfactory results. It achieves an average signal-to-noise-distortion (SNDR) of 14.51 at a spike compression ratio (SCR) of 30. Operated at a clock frequency of 192 kHz and a supply voltage of 1.8 V, the circuit consumes a power of 4.88 μ W and a silicon area of 0.14 mm2 per channel.

A Hardware-Efficient Novelty-Aware Spike Sorting Approach for Brain-Implantable Microsystems

Unsupervised spike sorting, a vital processing step in real-time brain-implantable microsystems, is faced with the prominent challenge of managing nonstationarity in neural signals. In long-term recordings, spike waveforms gradually change and new source neurons are likely to become activated. Adaptive spike sorters combined with on-implant training units effectively process the nonstationary signals at the cost of high hardware resource utilization. On the other hand, static approaches, while being hardware-friendly, are subjected to decreased processing performance in such recordings where the neural signal characteristics gradually change. To strike a balance between the hardware cost and processing performance, this study proposes a hardware-efficient novelty-aware spike sorting approach that is capable of dealing with both variated spike waveforms and spike waveforms generated from new source neurons. Its improved hardware efficiency compared to adaptive ones and capability of dealing with nonstationary signals make it attractive for implantable applications. The proposed novelty-aware spike sorting especially would be a good fit for brain-computer interfaces where long-term, real-time interaction with the brain is required, and the available on-implant hardware resources are limited. Our unsupervised spike sorting benefits from a novelty detection process to deal with neural signal variations. It tracks the spike features so that in case of detecting an unexpected change (novelty detection) both on and off-implant parameters are updated to preserve the performance in new state. To make the proposed approach agile enough to be suitable for brain implants, the on-implant computations are reduced while the computational burden is realized off-implant. The performance of our proposed approach is evaluated using both synthetic and real datasets. The results demonstrate that, in the mean, it is capable of detecting 94.31% of novel spikes (wave-drifted or emerged spikes) with a classification accuracy (CA) of 96.31%. Moreover, an FPGA prototype of the on-implant circuit is implemented and tested. It is shown that in comparison to the OSORT algorithm, a pivotal spike sorting method, our spike sorting provides a higher CA at significantly lower hardware resources. The proposed circuit is also implemented in a 180-nm standard CMOS process, achieving a power consumption of 1.78[Formula: see text][Formula: see text] per channel and a chip area of 0.07[Formula: see text]mm2 per channel.

A Vector Quantization-Based Spike Compression Approach Dedicated to Multichannel Neural Recording Microsystems

Implantable high-density multichannel neural recording microsystems provide simultaneous recording of brain activities. Wireless transmission of the entire recorded data causes high bandwidth usage, which is not tolerable for implantable applications. As a result, a hardware-friendly compression module is required to reduce the amount of data before it is transmitted. This paper presents a novel compression approach that utilizes a spike extractor and a vector quantization (VQ)-based spike compressor. In this approach, extracted spikes are vector quantized using an unsupervised learning process providing a high spike compression ratio (CR) of 10-80. A combination of extracting and compressing neural spikes results in a significant data reduction as well as preserving the spike waveshapes. The compression performance of the proposed approach was evaluated under variant conditions. We also developed new architectures such that the hardware blocks of our approach can be implemented more efficiently. The compression module was implemented in a 180-nm standard CMOS process achieving a SNDR of 14.49[Formula: see text]dB and a classification accuracy (CA) of 99.62% at a CR of 20, while consuming 4[Formula: see text][Formula: see text]W power and 0.16[Formula: see text]mm² chip area per channel.

Compressed Sensing of Extracellular Neurophysiology Signals: A Review

This article presents a comprehensive survey of literature on the compressed sensing (CS) of neurophysiology signals. CS is a promising technique to achieve high-fidelity, low-rate, and hardware-efficient neural signal compression tasks for wireless streaming of massively parallel neural recording channels in next-generation neural interface technologies. The main objective is to provide a timely retrospective on applying the CS theory to the extracellular brain signals in the past decade. We will present a comprehensive review on the CS-based neural recording system architecture, the CS encoder hardware exploration and implementation, the sparse representation of neural signals, and the signal reconstruction algorithms. Deep learning-based CS methods are also discussed and compared with the traditional CS-based approaches. We will also extend our discussion to cover the technical challenges and prospects in this emerging field.

Multichannel parallel processing of neural signals in memristor arrays

Fully implantable neural interfaces with massive recording channels bring the gospel to patients with motor or speech function loss. As the number of recording channels rapidly increases, conventional complementary metal-oxide semiconductor (CMOS) chips for neural signal processing face severe challenges on parallelism scalability, computational cost, and power consumption. In this work, we propose a previously unexplored approach for parallel processing of multichannel neural signals in memristor arrays, taking advantage of their rich dynamic characteristics. The critical information of neural signal waveform is extracted and encoded in the memristor conductance modulation. A signal segmentation scheme is developed to adapt to device variations. To verify the fidelity of the processed results, seizure prediction is further demonstrated, with high accuracy above 95% and also more than 1000× improvement in power efficiency compared with CMOS counterparts. This work suggests that memristor arrays could be a promising multichannel signal processing module for future implantable neural interfaces.

Neural signal analysis with memristor arrays towards high-efficiency brain-machine interfaces

Brain-machine interfaces are promising tools to restore lost motor functions and probe brain functional mechanisms. As the number of recording electrodes has been exponentially rising, the signal processing capability of brain–machine interfaces is falling behind. One of the key bottlenecks is that they adopt conventional von Neumann architecture with digital computation that is fundamentally different from the working principle of human brain. In this work, we present a memristor-based neural signal analysis system, where the bio-plausible characteristics of memristors are utilized to analyze signals in the analog domain with high efficiency. As a proof-of-concept demonstration, memristor arrays are used to implement the filtering and identification of epilepsy-related neural signals, achieving a high accuracy of 93.46%. Remarkably, our memristor-based system shows nearly 400× improvements in the power efficiency compared to state-of-the-art complementary metal-oxide-semiconductor systems. This work demonstrates the feasibility of using memristors for high-performance neural signal analysis in next-generation brain–machine interfaces.

Designing energy efficient and high performance brain-machine interfaces with millions of recording electrodes for in-situ analysis remains a challenge. Here, the authors develop a memristor-based neural signal analysis system capable of filtering and identifying epilepsy-related brain activities with an accuracy of 93.46%.

A Software-Defined Radio Receiver for Wireless Recording From Freely Behaving Animals

To eliminate tethering effects on the small animals' behavior during electrophysiology experiments, such as neural interfacing, a robust and wideband wireless data link is needed for communicating with the implanted sensing elements without blind spots. We present a software-defined radio (SDR) based scalable data acquisition system, which can be programmed to provide coverage over standard-sized or customized experimental arenas. The incoming RF signal with the highest power among SDRs is selected in real-time to prevent data loss in the presence of spatial and angular misalignments between the transmitter (Tx) and receiver (Rx) antennas. A 32-channel wireless neural recording system-on-a-chip (SoC), known as WINeRS-8, is embedded in a headstage and transmits digitalized raw neural signals, which are sampled at 25 kHz/ch, at 9 Mbps via on-off keying (OOK) of a 434 MHz RF carrier. Measurement results show that the dual-SDR Rx system reduces the packet loss down to 0.12%, on average, by eliminating the blind spots caused by the moving Tx directionality. The system operation is verified in vivo on a freely behaving rat and compared with a commercial hardwired system.

On-Chip Neural Data Compression Based On Compressed Sensing With Sparse Sensing Matrices

On-chip neural data compression is an enabling technique for wireless neural interfaces that suffer from insufficient bandwidth and power budgets to transmit the raw data. The data compression algorithm and its implementation should be power and area efficient and functionally reliable over different datasets. Compressed sensing is an emerging technique that has been applied to compress various neurophysiological data. However, the state-of-the-art compressed sensing (CS) encoders leverage random but dense binary measurement matrices, which incur substantial implementation costs on both power and area that could offset the benefits from the reduced wireless data rate. In this paper, we propose two CS encoder designs based on sparse measurement matrices that could lead to efficient hardware implementation. Specifically, two different approaches for the construction of sparse measurement matrices, i.e., the deterministic quasi-cyclic array code (QCAC) matrix and -sparse random binary matrix [-SRBM] are exploited. We demonstrate that the proposed CS encoders lead to comparable recovery performance. And efficient VLSI architecture designs are proposed for QCAC-CS and -SRBM encoders with reduced area and total power consumption.