A Fully Integrated RF-Powered Energy-Replenishing Current-Controlled Stimulator

Development of Ocular Muscle Stimulation Systems and Optimization of Electrical Stimulus Parameters for Paralytic Strabismus Treatment

Paralysis of the extraocular muscles can lead to complications such as strabismus, diplopia, and loss of stereopsis. Current surgical treatments aim to mitigate these issues by resecting the paralyzed muscle or transposing the other recti muscles to the paralyzed muscle, but they do not fully improve the patient's quality of life. Electrical stimulation shows promise, while requiring further in vivo experiments and research on various stimulation parameters. In this study, we conducted experiments on rabbits to stimulate the superior rectus (SR) muscles using different parameters and stimulation waveforms. To provide various types of electrical stimulation, we developed the ocular muscle stimulation systems capable of both current controlled stimulation (CCS) and high-frequency stimulation (HFS), along with the chip that enables energy-efficient and safe switched-capacitor stimulation (SCS). We also developed electrodes for easy implantation and employed safe and efficient stimulation methods including CCS, SCS, and HFS. The in vivo animal experiments on normal and paralyzed SR muscles of rabbits showed that eyeball abduction angles were proportional to the current and pulse width of the stimulation. With the decaying exponential stimuli of the SCS system, eyeball abductions were 2.58× and 5.65× larger for normal and paralyzed muscles, respectively, compared to the rectangular stimulus of CCS. HFS achieved 0.92× and 0.26× abduction for normal and paralyzed muscles, respectively, with half energy compared to CCS. In addition, the continuous changes in eyeball abduction angle in response to varying stimulation intensity over time were observed.

Active Neural Interface Circuits and Systems for Selective Control of Peripheral Nerves: A Review

Interfaces with peripheral nerves have been widely developed to enable bioelectronic control of neural activity. Peripheral nerve neuromodulation shows great potential in addressing motor dysfunctions, neurological disorders, and psychiatric conditions. The integration of high-density neural electrodes with stimulation and recording circuits poses a challenge in the design of neural interfaces. Recent advances in active electrode strategies have achieved improved reliability and performance by implementing in-situ control, stimulation, and recording of neural fibers. This paper presents an overview of state-of-the-art neural interface systems that comprise a range of neural electrodes, neurostimulators, and bio-amplifier circuits, with a special focus on interfaces for the peripheral nerves. A discussion on the efficacy of active electrode systems and recommendations for future directions conclude this paper.

An Energy-Efficient Wireless Power Receiver With One-Step Adiabatic-Bipolar-Supply Generating for Implantable Electrical Stimulation Applications

This paper presents an energy-efficient wireless power receiver for implantable electrical stimulation applications, which can achieve one-step adiabatic bipolar-supply that is generated by a hybrid single-stage dual-output regulating (SSDOR) rectifiers. The structure using only four switches overcomes the disadvantages that the two output voltage values in the traditional dual-output rectifiers are close to each other. A constant-current (CC) controlled adiabatic dynamic voltage scaling (DVS) technique is proposed to minimize the voltage headroom of the stimulating drivers and improve the stimulation efficiency significantly. In addition, the receiver adopts only one general constant on-time (COT) low-frequency control to adjust the stimulation current, reducing both the power consumption and the complexity of the control circuits. The proposed receiver has been fabricated in a 0.18 μm BCD process with ±6 V voltage compliance and 2.5 mA maximum stimulating current. With a current range from ±1.5 mA to ±2.5 mA, the measured maximum average headroom voltage is only 80 mV and the peak total efficiency of the receiver is 85.6 %. The functionalities of the proposed receiver have been successfully verified through in vitro experiments.

Energy-Efficient Power Management Interface With Adaptive HV Multimode Stimulation for Power-Sensor Integrated Patch-Type Systems

An energy-efficient power management interface (PMI) with adaptive high-voltage (HV) stimulation capability is presented for patch-type healthcare devices where power management and sensor readout circuits are integrated. For efficient power supply, it proposes a multimode buck converter with an adaptive mode controller, delivering 95.6% peak power conversion efficiency and over 90% efficiency across a wide 4-440 mA output current range. For energy-efficient stimulation, a HV stimulation system is designed to perform mode-adaptive on/off control, where the charge pump (CP) is adopted for periodic power saving. The CP output is adaptively tuned to minimize the stimulator's power waste by utilizing a bio-impedance path in the sensor circuit. The stimulation core supports multimode functionality of current-/voltage-controlled stimulations with monopolar and bipolar modes, providing ten kinds of various stimulation waveform shape. For efficient system operation, battery interface circuits are included to monitor state-of-charge (SOC) conditions, and a device power adjustment scheme is proposed to provide SOC-based maximum 28% power reduced optimal operation of high-resolution and low-power. The power-sensor integrated circuits were fabricated in a 0.18-μm CMOS process, and the proposed schemes were experimentally verified. For system-level feasibility, a patch-type device prototype was manufactured, and both power and bio-signal interfaces were functionally demonstrated.

A 4-Channel Neural Stimulation IC Design With Charge Balancing and Multiple Current Output Modes

This article proposes a neural stimulation integrated circuit design with multiple current output modes. In the cathodic stimulation phase and anodic stimulation phase, each output current waveform can be independently selected to either exponential waveform or square wave, so the stimulator holds four stimulation modes. To minimize the headroom voltage of the output stage and enhance the power efficiency of the proposed stimulator, we introduce the exponentially decaying current which is realized by the exponential current generation circuit in this work. It can enhance the longer duration of the stimulation pulse as well. In case the residual charge may cause harm to patients, a charge balancing technique is implemented in this work for all operation modes. The four-channel stimulator IC is implemented in a 180-nm CMOS process, occupying a core area of 1.93 mm2. The measurement results show that the proposed stimulator realized a maximum power efficiency of 91.3% and the maximum stimulation duration is 3 times larger than previous works. Moreover, even in exponential output waveform mode, the maximum residual charge in a single cycle is only 255 pC due to the proposed charge balancing technique. The experiment results based on the PBS solution also show that the stimulator IC can remove residual charges within 60 μs, and the electrode voltage remains stable within a safe range under multicycle stimulation.

A resonant current-mode wireless power transfer for implantable medical devices: an overview

Implantable Medical Devices (IMDs) have been developing in ways to be lighter and lower-power systems. In the view of such developments, the battery recharging capacity to ensure the stable operation of the system is essential. Wireless power transfer (WPT) was proposed as a solution to recharge the battery without complex metallic contacts. However, due to limitations such as threshold voltage of power switches and minimal input power of the multi-stage structure (Rectifier + Regulator/DC-DC converter) of conventional voltage-mode (VM) WPT, there are drawbacks of an input power range above a certain threshold level and limitations due to strict regulations on the human body. These issues make the design of the IMD battery charger much harder and prevent IMDs from being a more viable option for people-in-need. This paper introduces distinguishing characteristics of resonant current-mode (RCM) WPT technology to overcome the aforementioned issues. It also describes the basic theory, conventional circuits of VM/RCM, comparisons, and major challenges of RCM. Finally, advanced and efficiency-enhancing techniques of the-state-of-art works among the RCM topologies will be discussed to follow up the trend of RCM WPT.

A Load-Insensitive Hybrid LSK Back Telemetry System With Slope-Based Demodulation for Inductively Powered Biomedical Devices

This paper presents a hybrid load-shift keying (LSK) modulation for a load-insensitive back telemetry system to realize near-constant voltage changes in a primary coil (L₁) against a wide range of load variations. The hybrid-LSK-enabled full-wave rectifier enables the sequential combination of open- and short-coil functions for hybrid-LSK modulation in addition to wireless power conversion operation. Load-insensitive L₁ voltage changes can be demodulated using the proposed slope- based demodulator, which utilizes the threshold slope of L₁ voltage changes over the back data pulse width, enabling robust data recovery regardless of the load conditions. The 0.56-mm² 0.18-μm standard CMOS hybrid-LSK prototype demonstrated that the variation of L₁ voltage changes could be minimized to 60 mV under load changes between 50 Ω and 50 kΩ at coil separation distance of 10 mm, achieving 88.2% reduction compared to the conventional short-coil LSK with 510 mV variation. The proposed back telemetry system also achieved a bit error rate (BER) of < 9.1 × 10^-10 under load ranges from 50 Ω to 50 kΩ and data rate of 1 Mbps, ensuring reliable back data recovery against load variations.

A Wireless Power and Data Transfer IC for Neural Prostheses Using a Single Inductive Link With Frequency-Splitting Characteristic

This paper presents a frequency-splitting-based wireless power and data transfer IC that simultaneously delivers power and forward data over a single inductive link. For data transmission, frequency-shift keying (FSK) is utilized because the FSK modulation scheme supports continuous wireless power transmission without disruption of the carrier amplitude. Moreover, the link that manifests the frequency-splitting characteristic due to a close distance between coupled coils provides wide bandwidth for data delivery without degrading the quality factors of the coils. It results in large power delivery, high data rate, and high power transfer efficiency. The presented IC fabricated in a 180-nm BCD process simultaneously achieves up-to-115-mW wireless power delivery to the load and 2.5-Mb/s downlink data rate over the single inductive link. The measured overall power efficiency from the DC power supply at the transmitter module to the load at the receiver module reaches 56.7 % at its maximum, and the bit error rate is lower than 10 ^-6 at 2.5 Mb/s. As a result, the figure of merit (FoM) for data transmission is enhanced by 2 times, and the FoM for power delivery is improved by 38.7 times compared to prior state-of-the-arts using a single inductive link.

Advances in Neural Recording and Stimulation Integrated Circuits

In the past few decades, driven by the increasing demands in the biomedical field aiming to cure neurological diseases and improve the quality of daily lives of the patients, researchers began to take advantage of the semiconductor technology to develop miniaturized and power-efficient chips for implantable applications. The emergence of the integrated circuits for neural prosthesis improves the treatment process of epilepsy, hearing loss, retinal damage, and other neurological diseases, which brings benefits to many patients. However, considering the safety and accuracy in the neural prosthesis process, there are many research directions. In the process of chip design, designers need to carefully analyze various parameters, and investigate different design techniques. This article presents the advances in neural recording and stimulation integrated circuits, including (1) a brief introduction of the basics of neural prosthesis circuits and the repair process in the bionic neural link, (2) a systematic introduction of the basic architecture and the latest technology of neural recording and stimulation integrated circuits, (3) a summary of the key issues of neural recording and stimulation integrated circuits, and (4) a discussion about the considerations of neural recording and stimulation circuit architecture selection and a discussion of future trends. The overview would help the designers to understand the latest performances in many aspects and to meet the design requirements better.

A Versatile Hermetically Sealed Microelectronic Implant for Peripheral Nerve Stimulation Applications

This article presents a versatile neurostimulation platform featuring a fully implantable multi-channel neural stimulator for chronic experimental studies with freely moving large animal models involving peripheral nerves. The implant is hermetically sealed in a ceramic enclosure and encapsulated in medical grade silicone rubber, and then underwent active tests at accelerated aging conditions at 100°C for 15 consecutive days. The stimulator microelectronics are implemented in a 0.6-μm CMOS technology, with a crosstalk reduction scheme to minimize cross-channel interference, and high-speed power and data telemetry for battery-less operation. A wearable transmitter equipped with a Bluetooth Low Energy radio link, and a custom graphical user interface provide real-time, remotely controlled stimulation. Three parallel stimulators provide independent stimulation on three channels, where each stimulator supports six stimulating sites and two return sites through multiplexing, hence the implant can facilitate stimulation at up to 36 different electrode pairs. The design of the electronics, method of hermetic packaging and electrical performance as well as in vitro testing with electrodes in saline are presented.

Energy-Efficient Integrated Circuit Solutions Toward Miniaturized Closed-Loop Neural Interface Systems

Miniaturized implantable devices play a crucial role in neural interfaces by monitoring and modulating neural activities on the peripheral and central nervous systems. Research efforts toward a compact wireless closed-loop system stimulating the nerve automatically according to the user's condition have been maintained. These systems have several advantages over open-loop stimulation systems such as reduction in both power consumption and side effects of continuous stimulation. Furthermore, a compact and wireless device consuming low energy alleviates foreign body reactions and risk of frequent surgical operations. Unfortunately, however, the miniaturized closed-loop neural interface system induces several hardware design challenges such as neural activity recording with severe stimulation artifact, real-time stimulation artifact removal, and energy-efficient wireless power delivery. Here, we will review recent approaches toward the miniaturized closed-loop neural interface system with integrated circuit (IC) techniques.

A 3 mm × 3 mm Fully Integrated Wireless Power Receiver and Neural Interface System-on-Chip

A miniaturized, fully integrated wireless power receiver system-on-chip with embedded 16-channel electrode array and data transceiver for electrocortical neural recording and stimulation is presented. An H-tree power and signal distribution network throughout the SoC maintains high quality factor up to 11 in the on-chip receiver coil at 144 MHz resonant frequency while rejecting RF interference in sensitive neural interface circuits owing to its perpendicular and equidistant geometry. A multi-mode buck-boost resonant regulating rectifier (B ²R ³) offers greater than 11-dB input dynamic range in RF reception and less than 1 mV overshoot in transient load regulation. At 10 mm link distance, the 9 mm ² neural interface SoC fabricated in a 180 nm silicon-on-insulator (SOI) process attains an overall wireless power transmission system efficiency (WSE) of 3.4% in driving a 160  μW load yielding a WSE figure-of-merit of 131, while maintaining signal integrity in analog recording and wireless data transmission that comprise the on-chip load.